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preliminary data sheet august 2005 truephy ? et1011 gigabit ethernet transceiver features q 10base-t, 100base-tx, and 1000base-t gigabit ethernet transceiver: ? 0.13 m process ? 128-pin tqfp and 84-pin mlcc: r rgmii, gmii, mii, rtbi, and tbi interfaces to mac or switch ? 68-pin mlcc: r rgmii and rtbi interfaces to mac or switch q low power consumption: ? typical power less than 750 mw in 1000base-t mode ? advanced power management ? acpi compliant wake-on-lan support q oversampling architecture to improve signal integ- rity and snr q optimized, extended performance echo and next filters q all digital baseline wander correction q digital pga control q on-chip diagnostic support q automatic speed negotiation q automatic speed downshift q single supply 3.3 v or 2.5 v operation: ? on-chip regulator controllers ? 3.3 v or 2.5 v digital i/o ? 1.0 v or 1.1 v core power supplies ? 1.8 v or 2.5 v for transformer center tap q jtag introduction agere systems et1011 is a gigabit ethernet trans- ceiver fabricated on a single cmos chip. packaged in either a 128-pin tqfp, an 84-pin mlcc, or a 68-pin mlcc, the et1011 is built on 0.13 m tech- nology for low power consumption and application in server and desktop nic cards. it features single power supply operation using on-chip regulator con- trollers. the 10/100/1000base-t device is fully com- pliant with ieee ? 802.3, 802.3u, and 802.3ab standards. the et1011 uses an oversampling architecture to gather more signal energy from the communication channel than possible with traditional architectures. the additional signal energy or analog complexity transfers into the digital domain. the result is an ana- log front end that delivers robust operation, reduced cost, and lower power cons umption than traditional architectures. using oversampling has allowed for the implementa- tion of a fractionally spac ed equalizer, which provides better equalization and has greater immunity to tim- ing jitter, resulting in be tter signal-to-noise ratio (snr) and thus improved ber. in addition, advanced timing algorithms are used to enable oper- ation over a wider range of cabling plants.
table of contents contents page contents page 2 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 features ......................................................................1 introduction..................................................................1 functional description .................................................5 oversampling architecture ....................................5 automatic speed downshift ..................................5 transmit functions ...............................................6 receive functions ................................................6 autonegotiation .....................................................7 carrier sense(128-pin tqfp and 84-pin mlcc only) .................................................................7 link monitor ..........................................................8 loopback mode ....................................................9 digital loopback ...................................................9 analog loopback ................................................10 leds ...................................................................11 regulator control ................................................11 resetting the et1011 .........................................11 low-power modes .............. ................................11 pin information ..........................................................12 pin diagram, 128-pin tqfp ..............................12 pin diagram, 68-pin mlcc ................................14 pin descriptions, 128-pi n tqfp, 84-pin mlcc, and 68-pin mlcc ............................................15 hardware interfac es ..................................................21 mac interface .....................................................22 management interface ........................................27 configuration interface........................................29 leds interface ....................................................33 media-dependent interface: transformer interface...........................................................34 clocking and reset .............................................35 jtag ...................................................................36 regulator control ................................................36 power, ground, and no connect ........................37 cable diagnostics......................................................38 register description ..................................................39 register address map ........................................39 register functions/settings ................................40 electrical specifications.............................................58 absolute maximum ratings ................................58 recommended operating conditions .................58 device electrical characteristics.........................60 timing specification ..................................................67 gmii 1000base-t transmit timing (128-pin tqfp only) ........................................67 gmii 1000base-t receive timing (128-pin tqfp only) ........................................68 rgmii 1000base-t transmit timing ..................69 rgmii 1000base-t receive timing ...................71 mii 100base-tx transmit timing .......................73 mii 100base-tx receive timing .......................74 mii 10base-t transmit timing........................... 75 mii 10base-t receive ti ming............................ 76 serial management interface timing ................. 77 reset timing ...................................................... 78 clock timing ...................................................... 79 jtag timing ...................................................... 80 package diagram, 128-pin tqfp ............................ 81 package diagram, 84-pin mlcc ............................ 82 package diagram, 68-pin mlcc ............................ 83 ordering information................................................. 84 related product documentation ....................... 84 table page table 1. agere systems et1011 device signals by interface, 128-pin tqfp, 84-pin and 68-pin mlcc ...................................... 15 table 2. multiplexed signals on the et1011.............. 20 table 3. gmii signal description (1000base-t mode) (128-pin tqfp and 84-p in mlcc only) ..... 22 table 4. rgmii signal description (1000base-t mode)................................... 23 table 5. mii interface (100base-tx and 10base-t) (128-pin tqfp and 84-pin mlcc only) .... 24 table 6. ten-bit interface (1000base-t) (128-pin tqfp and 84-pin mlcc only) .................. 25 table 7. rtbi signal description (1000base-t mode) .................................. 26 table 8. management frame structure ..................... 27 table 9. management interface ................................. 28 table 10. autonegotiation modes .............................. 29 table 11. master/slave pref erence............................ 30 table 12. mdi/mdi-x configuration........................... 31 table 13. configuration signals................................. 31 table 14. led ........................................................... 33 table 15. transformer interface signals.................... 34 table 16. clocking and reset.................................... 35 table 17. jtag test interface ................................... 36 table 18. regulator control interface........................ 36 table 19. supply voltage combinations .................... 37 table 20. power, ground, and no connect ............... 37 table 21. cable diagnostic functions .......................38 table 22. register address map ............................... 39 table 23. register type definition............................. 39 table 24. control register?address 0 ..................... 40 table 25. status register?address 1 .......................41 table 26. phy identifier register 1?address 2........42 table 27. phy identifier register 2?address 3........42 table 28. autonegotiation advertisement register? address 4 .................................................. 43
table of contents (continued) table page table page agere systems inc. 3 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 table 29. autonegotiation link partner ability register?address 5 .............................. 44 table 30. autonegotiation expansion register? address 6 ............................................... 45 table 31. autonegotiation next page transmit register?address 7 .............................. 45 table 32. link partner next page register? address 8 ............................................... 46 table 33. 1000 base-t control register? address 9 ............................................... 47 table 34. 1000base-t status register? address 10 ............................................. 48 table 35. reserved registers?addresses 11?14 .. 49 table 36. extended status register?address 15 .... 49 table 37. reserved registers?addresses 16?18.. 49 table 38. loopback control register?address 19 .. 50 table 39. reserved register s?address 20 ............. 50 table 40. management interface (mi) control register?address 21 ............................ 50 table 41. phy configuration register? address 22 ............................................. 51 table 42. phy control register?address 23 .......... 52 table 43. interrupt mask re gister?address 24 ....... 53 table 44. interrupt status register?address 25 ...... 54 table 45. phy status register?address 26 ............ 55 table 46. led control register 1?address 27........ 56 table 47. led control register 2?address 28........ 57 table 48. reserved registers?addresses 29?31.. 57 table 49. absolute maximum ratings....................... 58 table 50. et1011n0 and et1011r0 recommended operating conditions 1 ............................ 58 table 51. et1011n1 and et1011r1 recommended operating conditions 1 ............................ 59 table 52. device characteristics?3.3 v digital i/o supply (dvddio) ................................... 60 table 53. device characteristics?2.5 v digital i/o supply (dvddio) ................................... 60 table 54. et1011n0 and et1011r0 current consumption gmii 1000base-t............. 61 table 55. et1011n0 and et1011r0 current consumption gmii 100base-tx ............ 61 table 56. et1011n0 and et1011r0 current consumption gmii 10base-t................. 61 table 57. et1011n0 and et1011r0 current consumption gmii 10 base-t idle......... 62 table 58. et1011n0 and et1011r0 current consumption rgmii 1000base-t......... 62 table 59. et1011n0 and et1011r0 current consumption rgmii 100base-tx ........ 62 table 60. et1011n0 and et1011r0 current consumption rgmii 10base-t............. 63 table 61. et1011n0 and et1011r0 current consumption rgmii 10base-t idle ...... 63 table 62. et1011n1 and et1011r1 current consumption gmii 10 00base-t............. 64 table 63. et1011n1 and et1011r1 current consumption gmii 100base-tx ............ 64 table 64. et1011n1 and et1011r1 current consumption gmii 10base-t................. 64 table 65. et1011n1 and et1011r1 current consumption gmii 10 base-t idle......... 65 table 66. et1011n1 and et1011r1 current consumption rgmii 1000base-t......... 65 table 67. et1011n1 and et1011r1 current consumption rgmii 100base-tx ........ 65 table 68. et1011n1 and et1011r1 current consumption rgmii 10base-t............. 66 table 69. et1011n1 and et1011r1 current consumption rgmii 10base-t idle ...... 66 table 70. gmii 1000base-t transmit timing............ 67 table 71. gmii 1000base-t receive timing............. 68 table 72. rgmii 1000base-t transmit timing ......... 69 table 73. rgmii 1000base-t transmit timing ......... 70 table 74 . rgmii 1000base-t receive timing ......... 71 table 75. rgmii 1000base-t receive timing .......... 72 table 76. mii 100base-tx transmit timing .............. 73 table 77. mii 100base-tx receive timing ............... 74 table 78. mii 10base-t transmit timing................... 75 table 79. mii 10base-t re ceive timing ................... 76 table 80. serial management interface timing......... 77 table 81. reset timing.............................................. 78 table 82. clock timing .............................................. 79 table 83. jtag timing .............................................. 80 table 84. chip set names and part numbers .......... 84 table 85. related product documentation................ 84
table of contents (continued) figure page figure page 4 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 figure 1. et1011 block diagram................................. 5 figure 2. loopback functionality................................. 9 figure 3. digital loopback........................................... 9 figure 4. replica analog loopback........................... 10 figure 5. line driver analog loopback ..................... 10 figure 6. pin diagram for et1011 in 128-pin tqfp package (top view) ............................... 12 figure 7. pin diagram for et1011 in 84-pin mlcc package (top view) ............................... 13 figure 8. pin diagram for et1011 in 68-pin mlcc package (top view) ............................... 14 figure 9. et1011 gigabit ethernet card block diagram ........................................ 21 figure 10. gmii mac-phy signals ........................... 22 figure 11. rgmii mac-phy signals......................... 23 figure 12. mii signals................................................ 24 figure 13. ten-bit interface ....................................... 25 figure 14. reduced ten-bit interface........................ 26 figure 15. gmii 1000base-t transmit timing .......... 67 figure 16. gmii 1000base-t receive timing ........... 68 figure 17. rgmii 1000ba se-t transmit timing? trace delay ............................................ 69 figure 18. rgmii 1000ba se-t transmit timing? internal delay ......................................... 70 figure 19. rgmii 1000base-t receive timing? trace delay ............................................ 71 figure 20. rgmii 1000base-t receive timing? internal delay ......................................... 72 figure 21. mii 100base-tx transmit timing ............. 73 figure 22. mii 100base-tx receive timing.............. 74 figure 23. mii 10base-t transmit timing ................. 75 figure 24. mii 10base-t receive timing .................. 76 figure 25. serial manageme nt interface timing........ 77 figure 26. reset timing ............................................ 78 figure 27. clock timing............................................. 79 figure 28. jtag timing............................................. 80
preliminary data sheet august 2005 agere systems inc. 5 gigabit ethernet transceiver truephy et1011 functional description agere systems et1011 is a gigabit ethernet transceiver th at simultaneously transmits and receives on each of the four utp pairs of category 5 cable (signal dimensions or channels a, b, c, and d) at 125 msymbols/s using five- level pulse amplitude modulation (pam). figure 1 is a block diagram of its basic configuration. figure 1. et1011 block diagram pma a pcs next cancellers echo canceller transmit shaping ffe rgmii gmii mii rtbi tbi gain control timing control blw correction dac adc pga hybrid trellis decoder clock generator pma b pma c pma d trd[0-3] txd[7:0] rx_er rx_dv tx_en tx_er gtx_clk rxd[7:0] rx_clk clock management interface mi registers jtag/ test auto- negotiation leds/ config 10base-t mdc mdint_n mdio xtal_1 reset_n xtal_2 sys_clk leds col crs tck trst_n tms tdo tdi config phyad[4:0] bias rset pma b reset tx_clk oversampling architecture the et1011 architecture uses oversampling tech- niques to sample at two times the symbol rate. a frac- tionally spaced feed forward equalizer (ffe) adapts to remove intersymbol interference (isi) and to shape the spectrum of the received si gnal to maximize the (snr) at the trellis decoder in put. the ffe equalizes the channel to a fixed target response. oversampling enables the use of a fractionally spaced equalizer (fse) structure for the ffe, resulting in symbol rate clocking for both the ffe and the rest of the receiver. this provides robust operation and substantial power savings. automatic speed downshift automatic speed downshift is an enhanced feature of autonegotiation that allows the et1011 to: q fallback in speed, based on cabling conditions or link partner abilities. q operate over cat-3 cabling (in 10base-t mode). q operate over two-pair cat-5 cabling (in 100base-tx mode). for speed fallback, the et1011 first tries to autonegoti- ate by advertising 1000base-t capability. after a num- ber of failed attempts to bring up the link, the et1011 falls back to advertising 100base-tx and restarts the autonegotiation process. this process continues through all speeds down to 10base-t. at this point, there are no lower speeds to try and so the host enables all technologies and starts again. phy configuration register, address 22, bits 11and 10 enable automatic speed downshift and specifies if fall- back to 10base-t is allowed. phy control register, address 23, bits 11and 12 specify the number of failed attempts before downshift (programmable to 1, 2, 3, or 4 attempts).
6 6 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 functional description (continued) transmit functions 1000base-t encoder in 1000base-t mode, the et1011 translates 8-bit data from the mac interfaces into a code group of four qui- nary symbols that are then transmitted by the pma as 4d five-level pam signals over the four pairs of cat-5 cable. 100base-tx encoder in 100base-tx mode, 4-bit data from the media inde- pendent interface (mii) is 4b/5b encoded to output 5-bit serial data at 125 mhz. the bit stream is sent to a scrambler, and then encoded to a three-level mlt3 sequence that is then transmitted by the pma. 10base-t encoder in 10base-t mode, the et1011 transmits and receives manchester-encoded data. receive functions decoder 1000base-t in 1000base-t mode, the pma recovers the 4d pam signals after compensating for the cabling conditions. the resulting code group is decoded to 8-bit data. data stream delimiters are translated appropriately, and the data is output to the receive data pins of the mac interfaces. the gmii receive error signal is asserted when invalid code groups are detected in the data stream. decoder 100base-tx in 100base-tx mode, the pma recovers the three- level mlt3 sequence that is descrambled and 5b/4b decoded to 4-bit data. this is output to the mii receive data pins after data stream delimiters have been trans- lated appropriately. the mii receive error signal is asserted when invalid code groups are detected in the data stream. decoder 10base-t in 10base-t mode, the et1011 decodes the manches- ter-encoded received signal. hybrid the hybrid subtracts the tr ansmitted signal from the input signal allowing full-duplex operation on each of the twisted-pair cables. programmable gain amplifier (pga) the pga operates on the received signal in the analog domain prior to the analog-to-digital converter (adc). the gain control module monitors the signal at the out- put of the adc in the digital domain to control the pga. it implements a gain that maximizes the signal at the adc while ensuring that no hard clipping occurs. clock generator a clock generator circuit uses the 25 mhz input clock signal and a phase-locked loop (pll) circuit to gener- ate all the required internal analog and digital clocks. a 125 mhz system clock is also generated and is avail- able as an output clock. analog-to-digital converter the adc operates at 250 mhz oversampling at twice the symbol rate in 1000base-t and 100base-tx. this enables innovative timing recovery and fractional skew correction and has allowed transfer of analog complex- ity to the digital domain. timing recovery/generation the timing recovery and generator block creates trans- mit and receive clocks for a ll modes of operation. in transmit mode, the 10base-t and 100base-tx modes use the 25 mhz clock input. while in receive mode, the input clock is locked to the receive data stream. 1000base-t is implemented using a master-slave tim- ing scheme, where the master transmit and receive are locked to the 25 mhz clock input, and the slave acquires timing information from the receive data stream. timing recovery is accomplished by first acquiring lock on one channel and then making use of the constant phase relationship between channels to lock on the other pairs, resu lting in a simplified pll architecture. timing shifts due to changing environ- mental conditions are tracked by the et1011.
agere systems inc. 7 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 functional description (continued) adaptive fractionally spaced equalizer the et1011?s unique oversampling architecture employs an fse in place of the traditional ffe struc- ture. this results in robust equalization of the commu- nications channel, which translates to superior bit error rate (ber) performance over the widest variety of worst-case cabling scenarios. the all-digital equalizer automatically adapts to changing conditions. echo and crosstalk cancellers since the four twisted pairs are bundled together and not insulated from each other in gigabit ethernet, each of the transmitted signals is coupled onto the three other cables and is seen at the receiver as near-end crosstalk (next). a hybrid circuit is used to transmit and receive simultaneously on each pair. if the trans- mitter is not perfectly matched to the line, a signal com- ponent will be reflected back as an echo. reflections can also occur at other conn ectors or cable imperfec- tions. the et1011 cancels echo and next by sub- tracting an estimate of these signals from the equalizer output. baseline wander correction a known issue for 1000base-t and 100base-tx is that the transformer attenuates at low frequencies. as a result, when a large number of symbols of the same sign are transmitted consecutively, the signal at the receiver gradually dies away. this effect is called base- line wander. by employing a circuit that continuously monitors and compensates for this effect, the probabil- ity of encountering a receiv e symbol error is reduced. autonegotiation autonegotiation is implemented in accordance with ieee 802.3. the device supports 10base-t, 100base- tx, and 1000base-t and can autonegotiate between them in either half- or fu ll-duplex mode. it can also par- allel detect 10base-t or 100base-tx. if autonegotia- tion is disabled, a 10base-t or 100base-tx link can be manually selected via the ieee mii registers. pair skew correction in gigabit ethernet, pair skew (timing differences between pairs of cable) can result from differences in length or manufacturing vari ations between the four individual twisted-pair cables. the et1011 automati- cally corrects for both integer and fractional symbol tim- ing differences between pairs. automatic mdi crossover during autonegotiation, the et1011 automatically detects and sets the required mdi configuration so that the remote transmitter is connected to the local receiver and vice versa. this eliminates the need for crossover cables or crosswired (mdix) ports. if the remote device also implem ents automatic mdi cross- over, and/or the crossover is implemented in the cable, the crossover algorithm ensures that only one element implements the required crossover. polarity inversion correction in addition to automatic mdi crossover that is neces- sary for autonegotiation, 10base-t, and 100base-tx operation, the et1011 automatically corrects crossover of the additional two pairs used in 1000base-t. polarity inversion on all pairs is also corrected. both of these effects may arise if the cabling has been incorrectly wired. carrier sense (128-pin tqfp and 84-pin mlcc only) the carrier sense signal (crs ) of the mac interface is asserted by the et1011 whenever the receive medium is nonidle. in half-duplex mode, crs may also be asserted when the transmit medium is nonidle. the crs may be enabled on transmit in half-duplex mode by writing to the phy configuration register, address 22, bit 15.
8 8 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 functional description (continued) link monitor 1000base-t once 1000base-t is autonegotiated and the link is established, both link partners continuously monitor their local receiver status. if the master device deter- mines a problem with its receiver, it signals the slave and both devices cease transmitting data but transmit idle. if the master retrains its receiver within 750 ms, then normal operation recommences. otherwise, both devices restart autonegotiation. if the slave device determines a problem with its receiver, it ceases transmitting and expects the master to transmit the idle sequence. if the slave retrains its receiver within 350 ms, normal operation recom- mences when the master sign als that its receiver is ready. if either receiver fails to reacquire, then autone- gotiation is restarted. 100base-tx in 100base-tx mode, the et1011 monitors the link and determines the link quality based on signal energy, mean square error and scrambler lock. if the link qual- ity is deemed insufficient, transmit and receive data are disabled. if the link had been autonegotiated then con- trol is handed back to autonegotiation. if the link had been manually set, the 100base-tx receiver is retrained, and the transmitter is set to transmit idle. once the link quality has bee n recovered, data transmit and receive are enabled. 10base-t in 10base-t mode, the et1011 monitors the link and determines the link quality based either on the pres- ence of valid link pulses or valid 10baset packets. if the link is deemed to have failed and the link had been autonegotiated, then control is handed back to autone- gotiation. if the link had been manually set, the et1011 continues to try to reestablish the link.
agere systems inc. 9 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 functional description (continued) loopback mode enabling loopback mode allows in-circuit testing of the et1011's digital and analog data path. the et1011 provides several options for loopback that te st and verify various functional blocks within the phy. these are digital loopback and analog loopback. figure 2 is a block diagram that shows the phy loopback func- tionality. figure 2. loopback functionality the loopback mode is selected by setting the respective bit in the phy loopback control register, mii register address 19. the default loopback mode is digital mii loo pback. loopback is enabled by writing to the phy control register, address 0, bit 14. digital loopback digital loopback provides the ability to loop the transmitted data back to the re ceiver via the digital circuitry. the point at which the signal is looped back is selected usin g the loopback control register with the following options being provided: mii and all digital. selecting the mii opti on gives a simple loopback with minimal latency where the data is looped back directly at the media-independent interf ace. this loopback is current ly set as the default, but it should be noted that it only exercises a small percentage of the phy circuitry. when the all-digital option is selected, the transmitted data is looped back at the interf ace between the digital and t he analog circuitry, thereby exercising a high percentage of the digital logic. figure 3 shows a block diagram of digital loopback. figure 3. digital loopback mac / switch phy digital phy afe remote phy replica loopback all digital loopback line driver loopback g m i i mii loopback mac / switch phy digital phy afe g m i i
10 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 functional description (continued) analog loopback analog loopback provides the ability to loop the transmitted signal back to the receiver withi n the afe. the point at which the signal is looped back is selected using the loo pback control register with the following options being pro- vided: replica and line driver. selecting the replica option causes the transmitted signal to be looped back through the replica generation circuitry of the on-chip hybrid, thereby allowing most of the digital and analog circuitry to be exercised. this loopback mode may be used even when the device is connected to a ne twork because nothing is transmitted to or received from the mdi in this case. the most thorough loopback test available without the cooper ation of a link partner is pr ovided by selecting the line driver option where the phy transmits to and receives from the mdi. however, in general, this loopback may not be used when the device is connected to a network because it could cause an unanticipated response from the link partner. figure 4 shows a block diagram of replica analog loopback and figure 5 shows a block diagram of line driver analog loopback. figure 4. replica analog loopback figure 5. line driver analog loopback mac / switch phy digital phy afe g m i i mac / switch phy digital phy afe rj-45 g m i i
agere systems inc. 11 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 functional description (continued) leds seven status leds are provided. these can be used to indicate speed of operation, duplex mode, link status, etc. there is a very high degree of programmability allowed. hence, the leds can be programmed to dif- ferent status functions from their default value, or they can be controlled directly from the mii register inter- face. the led signal pins can also be used for gen- eral-purpose i/o if not needed for led indication. note : the 68-pin mlcc and 84-pin mlcc have only two leds. both can be programmed through mii register 28 to provide all speed indications as well as link and activity indications. regulator control the et1011 has two on-chip regulator controllers. this allows the device to be powered from a single supply, either 3.3 v or 2.5 v. the on-chip regulator control cir- cuits provide output control voltages that can be used to control two external tran sistors and thus provide reg- ulated 1.0 v and 2.5 v supplies. resetting the et1011 the et1011 provides the abilit y to reset the device by hardware (pin r eset_n) or via soft ware through the management interface. a hardware reset is accom- plished by driving the active-low pin reset_n to 0 volts for a minimum of 20 s. the configuration pins and the physical address conf iguration are read during a hardware reset. a software reset is accomplished by setting bit 15 of the control register (mii register address 0 bit 15). the configuration pins and the physical address configura- tion are not read during software reset. low-power modes the et1011 supports a number of powerdown modes. hardware powerdown mode hardware powerdown is entered when the coma sig- nal is driven high. in hardware powerdown, all phy functions (analog and digital) are disabled. during hardware powerdown, sys_clk is not available and the mii registers are not accessible. at exit from hardware powerdown, the et1011 does the following: q initializes all analog circuits including the pll. q initializes all digital logic and state machines. q reads and latches the phy address pins. q initializes all mii registers to their default values (h/w configuration pins are reread). software powerdown mode software powerdown is entered when bit 11 of the con- trol register (mii register addre ss 0 bit 11) is set. in soft- ware powerdown, all phy functions except the serial management interface and clock circuitry are disabled. the mii registers can be read or written. if the system clock output is enabled (mii register address 22 bit 4), the 125 mhz system clock will still be available for use by the mac on pin sys_clk. at exit from software powerdown, the et1011 does the following: q initializes all digital logic and state machines. note: at exit from software powerdown, the h/w con- figuration pins and the phy address pins are not reread and the mii registers are not reset to their default values. thes e operations are only done during reset or recovery from hardware powerdown. wake-on-lan powerdown mode acpi power consumption compliant wake-on-lan mode is implemented on the et1011 by using the ieee standard mii registers to put the phy into 10base-t or 100base-tx modes. clearing the advertisement of 1000base-t (mii register address 9 bits 8, 9) and set- ting the desired 10base-t and 100base-tx advertise- ment (mii register address 4 bits 5-8) activates this feature. this must be follo wed by an autonegotiation restart via the control register (mii register address 0 bit 9). low-power energy-detect mode when coma is asserted, low-power energy-detect (lped) mode is enabled if l ped_en_n is low. in this mode, the phy monitors the cable for energy. if energy is detected, the mdint_n pin is asserted. the phy exits from lped mode when coma is deasserted. .
12 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information pin diagram, 128-pin tqfp figure 6. pin diagram for et1011 in 128-pin tqfp package (top view) dvss rx_er/rxd[9] dvddio 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 vdd dvss txd[3] txd[4] txd[5] txd[6] txd[7] dvss dvddio tck vdd dvss dvss trst_n tms/sys_clk_en_n tdi/lped_en_n tdo mac_if_sel[0] mac_if_sel[1] mac_if_sel[2] auto_mdi_en vdd dvss nc coma vdd dvss avddl avss avddh clk_in/xtal_1 xtal_2 avss reset_n nc nc nc nc 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 nc nc phyad[4] phyad[3] phyad[2] phyad[1] phyad[0] dvss vdd led_act/mdix_sel led_dup/duplex dvss vdd_reg ctrl_2v5 ctrl_1v0 dvss vdd led_1000/speed_1000 led_100/speed_100 led_10/speed_10 led_lnk/pause led_col/mas_cfg pres dvddio mdint_n mdio mdc vdd dvss sys_clk dvss dvddio rxd[7] rxd[6] rxd[5] rxd[4] dvss vdd 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 dvss dvddio rxd[3] rxd[2] rxd[1] rxd[0] rx_dv/rxd[8]/rx_ctl rx_clk/pma_rx_clk[0]/rxc nc col/pma_rx_clk1 crs/comma dvss tx_clk dvddio dvss gtx_clk/pma_tx_clk/txc nc dvss tx_er/txd[9] tx_en/txd[8]/tx_ctl txd[0] txd[1] txd[2] 104 agere systems et1011 trd[0]+ avss trd[0]? avss avddl nc trd[1]+ avss trd[1]? avss avddl avss avddh rset avddl trd[2]+ avss trd[2]? avss avddl nc trd[3]+ avss trd[3]? avss avddl
agere systems inc. 13 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information (continued) pin diagram, 84-pin mlcc figure 7. pin diagram for et1011 in 84-pin mlcc package (top view) 1 txd[5] 2 txd[6] 3 txd[7] 4 dvddio 5 tck 6 vdd 7 nc 8 nc 9 nc 10 nc 11 nc 12 trst_n 13 tms/sys_clk_en_n 14 tdi/lped_en_n 15 tdo 16 mac_if_sel[0] 17 mac_if_sel[1] 18 mac_if_sel[2] 19 vdd 20 avddl 21 avddh 84 txd[4] 83 txd[3] 82 txd[2] 81 txd[1] 80 txd[0] 79 tx_en/txd[8]/tx_ctl/txd[4] 78 tx_er/txd[9] 77 gtx_clk/pma_tx_clk/txc 76 dvddio 75 tx_clk 74 crs/comma 73 col/pma_rx_clk[1] 72 rx_clk/pma_rx_clk[0]/rxc 71 dvddio 70 rx_er/rxd[9] 69 rx_dv/rxd[8]/rx_ctl/rxd[4] 68 rxd[0] 67 rxd[1] 66 rxd[2] 65 rxd[3] 64 dvddio 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 clk_in/xtal_1 xtal_2 reset_n trd[0]+ trd[0]- avddl trd[1]+ trd[1]- avddl avddh rset avddl trd[2]+ trd[2]- avddl trd[3]+ trd[3]- avddl phyad[4] phyad[3] phyad[2] 63 vdd 62 rxd[4] 61 rxd[5] 60 rxd[6] 59 rxd[7] 58 dvddio 57 sys_clk 56 vdd 55 mdc 54 mdio 53 mdint_n 52 dvddio 51 pres 50 led_lnk/pause 49 led_1000/speed_1000 48 vdd 47 ctrl_1v0 46 ctrl_2v5 45 vdd_reg 44 phyad[0] 43 phyad[1] agere systems et1011 exposed pad (dvss and avss)
14 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information (continued) pin diagram, 68-pin mlcc figure 8. pin diagram for et1011 in 68-pin mlcc package (top view) dvddio sys_clk vdd mdc mdio mdint_n dvddio pres led_lnk/pause led_1000/speed_1000 vdd ctrl_1v0 ctrl_2v5 vdd_reg phyad[0] phyad[1] phyad[2] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 dvddio tck vdd dvss trst_n tms/sys_clk_en_n tdi/lped_en_n tdo mac_if_sel[0] mac_if_sel[1] vdd coma vdd avddl avddh clk_in/xtal_1 xtal_2 et1011 txd[3] txd[2] txd[1] txd[0] tx_ctl txc dvddio tx_clk rxc dvddio rx_ctl rxd[0] rxd[1] rxd[2] rxd[3] dvddio vdd reset_n trd[0]+ trd[0]? avddl trd[1]+ trd[1]? avddl avddh rset avddl trd[2]+ trd[2]? avddl trd[3]+ trd[3]? avddl phyad[3] agere systems exposed pad (dvss and avss) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 ?
agere systems inc. 15 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information (continued) pin descriptions, 128-pin tqfp, 84-pin mlcc, and 68-pin mlcc table 1. agere systems et1011 device signals by interface, 128-pin tqfp, 84-pin and 68-pin mlcc name description pad type internal pull-up/ pull-down 3-state analog pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc mac: gmii?gigabit media inde pendent interface (128-pin tqfp and 84-pin mlcc only) gtx_clk gmii transmit clock i ? ? ? 121 77 ? tx_er transmit error i ? ? ? 124 78 ? tx_en transmit enable i ? ? ? 125 79 ? txd[7:0] transmit data bits i ? ? ? 7, 6, 5, 4, 3 128, 127, 126 3, 2, 1, 84, 83, 82, 81, 80 ? rx_clk receive clock o ? z ? 113 72 ? rx_er receive error o ? z ? 110 70 ? rx_dv receive data valid o ? z ? 109 69 ? rxd[7:0] receive data bits o ? z ? 97, 98, 99, 100, 105, 106, 107, 108 59, 60, 61, 62, 65, 66, 67, 68 ? crs carrier sense o ? z ? 116 74 ? col collision detect o ? z ? 115 73 ? mac: rgmii?reduced gigabit media independent interface txc rgmii transmit clock i ? ? ? 121 77 63 txd[3:0] transmit data bits i ? ? ? 3, 128, 127, 126 83, 82, 81, 80 68, 67, 66, 65 tx_ctl transmit control i ? ? ? 125 79 64 rxc receive clock o ? z ? 113 72 60 rxd[3:0] receive data bits o ? z ? 105, 106, 107, 108 65, 66, 67, 68 54, 55, 56, 57 rx_ctl receive control o ? z ? 109 69 58 mac: mii?media independent interface (128-pin tqfp and 84-pin mlcc only) tx_clk mii transmit clock o ? z ? 118 75 ? tx_er transmit error i ? ? ? 124 78 ? tx_en transmit enable i ? ? ? 125 79 ? txd[3:0] transmit data bits i ? ? ? 3, 128, 127, 126 83, 82, 81, 80 ? rx_clk receive clock o ? z ? 113 72 ? rx_er receive error o ? z ? 110 70 ? rx_dv receive data valid o ? z ? 109 69 ? rxd[3:0] receive data bits o ? z ? 105, 106, 107, 108 65, 66, 67, 68 ? crs carrier sense o ? z ? 116 74 ? col collision detect o ? z ? 115 73 ?
16 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information (continued) pin descriptions, 128-pin tqfp, 84-pin mlcc, and 68-pin mlcc (continued) table 1. agere systems et1011 device signals by interface, 128-pin tqfp, 84-pin and 68-pin mlcc (cont.) name description pad type internal pull-up/ pull-down 3-state analog pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc mac: tbi?ten-bit interface (128-p in tqfp and 84-pin mlcc only) pma_ tx_clk tbi transmit clock i ? ? ? 121 77 ? txd[9:0] transmit data bits i ? ? ? 124, 125, 7, 6, 5, 4, 3, 128, 127, 126 78, 79, 3, 2, 1, 84, 83, 82, 81, 80, ? pma_rx_clk[0] tbi receive clock o ? z ? 113 72 ? rxd[9:0] receive data bits o ? z ? 110, 109, 97, 98, 99, 100, 105, 106, 107, 108 70, 69, 59, 60, 61, 62, 65, 66, 67, 68, ? pma_rx_ clk[1] tbi receive clock o ? z ? 115 73 ? comma valid comma detect i ? ? ? 116 74 ? mac: rtbi?reduced ten-bit interface txc rtbi transmit clock i ? ? ? 121 77 63 txd[3:0] transmit data bits i ? ? ? 3, 128, 127, 126 83, 82, 81, 80, 68, 67, 66, 65 tx_ctl transmit control i ? ? ? 125 79 64 rxc rtbi receive clock o ? z ? 113 72 60 rxd[3:0] receive data bits o ? z ? 105, 106, 107, 108 65, 66, 67, 68 54, 55, 56, 57 rx_ctl receive control o ? z ? 109 69 58 mdi: transformer interface trd[0]+ transmit and receive differential pair i/o ? ? a 39 25 19 trd[0]? 41 26 20 trd[1]+ transmit and receive differential pair i/o ? ? a 45 28 22 trd[1]? 47 29 23 trd[2]+ transmit and receive differential pair i/o ? ? a 54 34 28 trd[2]? 56 35 29 trd[3]+ transmit and receive differential pair i/o ? ? a 60 37 31 trd[3]? 62 38 32 rset analog reference resistor i/o ? ? a 52 32 26
agere systems inc. 17 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information (continued) pin descriptions, 128-pin tqfp, 84-pin mlcc, and 68-pin mlcc (continued) table 1. agere systems et1011 device signals by interface, 128-pin tqfp, 84-pin and 68-pin mlcc (cont.) 1. configuration signals are multiplexed wi th the led controls. during a reset, the stat us of the configuration pins are latche d and used to set the configuration and later to select the polarity to drive the leds. name description pad typ e internal pull-up/ pull-down 3-state analog pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc management interface phyad[4:0] phy address 4?1 i pull-down ? ? 67, 68, 69, 70, 71 40, 41, 42, 43, 44 34, 35, 36, 37 phyad [3:0] phy address 0 i pull-up ? ? mdc management interface clock i pull-down ? ? 91 55 48 mdio management data i/o i/o pull-up ? ? 90 54 47 mdint_n management interface interrupt o ? ? ? 89 53 46 configuration 1 speed_1000 1000base-t speed select i pull-up ? ? 82 49 42 speed_100 100base-tx spee d select i pull-up ? ? 83 ? ? speed_10 10base-t speed select i pull-up ? ? 84 ? ? duplex half- or full-duplex config- uration i pull-up ? ? 75 ? ? mas_cfg master slave conf iguration i pull-down ? ? 86 ? ? pause pause mode i pull-down ? ? 85 50 43 auto_mdi_en auto-mdi detection enable i pull-up ? ? 21 ? ? mdix_sel mdi/mdi-x selection i pull-down ? ? 74 ? ? mac_if_sel[0] mac interface select 0 i pull-down ? ? 18 16 9 mac_if_sel[1] mac interface select 1 i pull-down ? ? 19 17 10 mac_if_sel[2] mac interface select 2 i pull-down ? ? 20 18 ? sys_clk_en_n system clock enable i pull-up ? ? 15 13 6 lped_en_n low power energy detection enable i pull-up ? ? 16 14 7 pres precision resistor i ? ? ? 87 51 44
18 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information (continued) pin descriptions, 128-pin tqfp, 84-pin mlcc, and 68-pin mlcc (continued) 1. configuration signals are multiplexed with the led controls. during a reset, the stat us of the configuration pins are latche d and used to set the configuration and later to select the polarity to drive the leds. table 1. agere systems et1011 device signals by interface, 128-pin tqfp, 84-pin and 68-pin mlcc (cont.) name description pad type internal pull-up/ pull-down 3-state analog pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc led interface led_1000 1000base-t led o pull-up ? ? 82 49 42 led_100 100base-tx led o pull-up ? ? 83 ? ? led_10 10base-t led o pull-up ? ? 84 ? ? led_dup duplex led o pull-up ? ? 75 ? ? led_lnk link established led o pull-down ? ? 85 50 43 led_col collision led o pull-down ? ? 86 ? ? led_act transmit and receive activity o pull-down ? ? 74 ? ? jtag tck test clock i pull-up ? ? 10 5 2 trst_n test reset i pull-down ? ? 14 12 5 tms test mode select i pull-up ? ? 15 13 6 tdi test data input i pull-up ? ? 16 14 7 tdo test data output o pull-up ? ? 17 15 8 clocking and reset clk_in reference clock input i/o ? ? a 31 22 16 xtal_1 reference crystal input i/o ? ? a 31 22 16 xtal_2 reference crystal i/o ? ? a 32 23 17 sys_clksystem clock o???945750 reset_n reset i ? ? ? 34 24 18 coma hardware powerdown i pull-down ? ? 25 ? 12 regulator control ctrl_1v0 regulator control 1.0 v o ? ? a 79 47 40 ctrl_2v5 regulator control 2.5 v o ? ? a 78 46 39
agere systems inc. 19 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information (continued) pin descriptions, 128-pin tqfp, 84-pin mlcc, and 68-pin mlccc (continued) 1. configuration signals are multiplexed wi th the led controls. during a reset, the stat us of the configuration pins are latche d and used to set the configuration and later to select the polarity to drive the leds. 2. for the 84-pin and 68-pin mlcc, all avss and dvss pins shar e a common ground pin (pad) in the center of the device. table 1. agere systems et1011 device signals by interface, 128-pin tqfp, 84-pin and 68-pin mlcc (cont.) name description pad type internal pull-up/ pull-down 3-state analog pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc power, ground, and no connect vdd_reg regulator 2.5 v or 3.3 v supply v dd ??? 77 4538 dvddio digital i/o 2.5 v or 3.3 v supply v dd ? ? ? 9, 88, 96, 104, 111, 119 4, 52, 58, 64, 71, 76 1, 45, 51, 53, 59, 62 vdd digital core 1.0 v supply v dd ? ? ? 1, 11, 22, 26, 73, 81, 92, 102 6, 19, 48, 56, 63 3, 11, 13, 41, 49, 52 dvss 2 digital ground v ss ? ? ? 2, 8, 12, 13, 23, 27, 72, 76, 80, 93, 95, 101, 103, 112, 117, 120, 123 ?4 avddh analog power 2.5 v v dd ? ? ? 30, 51 21, 31 15, 25 avddl analog power 1.0 v v dd ? ? ? 28, 43, 49, 53, 58, 64 20, 27, 30, 33, 36, 39 14, 21, 24, 27, 30, 33 avss 2 analog ground v ss ? ? ? 29, 33, 40, 42, 46, 48, 50, 55, 57, 61, 63 ?? nc reserved?do not connect ? ? ? ? 24, 35, 36, 37, 38, 44, 59, 65, 66, 114, 122 7, 8, 9, 10, 11 ?
20 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 pin information (continued) pin descriptions, 128-pin tqfp, 84-pin mlcc, and 68-pin mlcc table 2. multiplexed signals on the et1011 default pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc alternate col 115 73 ? col 1, 6 pma_rx_clk[1] 2 crs 116 74 ? crs 1, 6 comma 2 gtx_clk 121 77 ? gtx_clk 1 ? pma_tx_clk 2 63 txc 3, 4 led_act 74 ? ? led_act mdix_sel 5 led_col 86 ? ? led_col mas_cfg 5 led_dup 75 ? ? led_dup duplex 5 led_lnk 85 50 43 led_lnk pause 5 led_1000 82 49 42 led_1000 speed_1000 5 led_100 83 ? ? led_100 speed_100 5 led_10 84 ? ? led_10 speed_10 5 rx_clk 113 72 ? rx_clk 1, 6 ? pma_rx_clk[0] 2 60 rxc 3, 4 rx_er 110 70 ? rx_er 1, 6 rxd[9] 2 rx_dv 109 69 ? rx_dv 1, 6 ? rxd[8] 2 58 rx_ctl 3, 4 tdi 16 14 7 tdi lped_en_n 5 tms 15 13 6 tms sys_clk_en_n 5 tx_er 124 78 ? tx_er 1, 6 txd[9] 2 tx_en 125 79 ? tx_en 1, 6 ? txd[8] 2 64 tx_ctl 3, 4 xtal_1 31 22 16 xtal_1 clk_in 1. gmii signal. 2. tbi signal. 3. rgmii signal. 4. rtbi signal. 5. reset/configuration signal. 6. mii signal.
agere systems inc. 21 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces the following hardware interfaces are included on the et1011 gigabit ethernet transceiver: several of the pins of the mac interfac e are multiplexed, but they are designed to be interchangeable so that the device can change the mac interface once the transmission capabilities (1 000base-t, 100base-tx, and 10base- t) are established. the following diagram shows the various interfaces on ea ch et1011 and how they connect to the mac and other support devices in a typical application. figure 9. et1011 gigabit ethernet card block diagram q mac interfaces: ? gmii (128-pin tqfp only) ? rgmii ? mii (128-pin tqfp only) ? tbi (128-pin tqfp only) ? rtbi q media dependent interface q management interface q configuration interface q led interface q clock and reset signals q jtag interface q regulator control q power and ground signals et1011 tck trst_n tms tdo tdi led_10 mdc mdint_n mdio xtal_1 xtal_2 reset_n rset trd[0]+/- trd[1]+/- trd[2]+/- trd[3]+/- txd[7:0] rx_er rx_dv tx_en tx_er gtx_clk rxd[7:0] rx_clk col crs tx_clk phyad[4:0] coma mac_if_sel[2:0] mac led_100 led_1000 led_dup led_lnk led_act led_col ctrl_2v5 ctrl_1v0 2.5v power plane 1.0v power plane agere systems et1011 gigabit ethernet phy vdd_reg
22 22 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) mac interface the et1011 supports rgmii, gmii, mii, rtbi, and tbi interfaces to the mac. the mac interface mode is selected via the hardware configuration pins, mac_if_sel[2:0]. gigabit media independent interface (gmii) (128-pin tqfp only) the gmii is fully compliant with ieee 802.3 clause 35. the gmii interface mode is selected by setting the hardware configuration pins mac_if_sel[2:0] = 000. figure 10. gmii mac-phy signals mac phy col rx_er rx_dv rxd[7:0] crs tx_er gtx_clk txd[7:0] tx_en rx_clk table 3. gmii signal descript ion (1000base-t mode) (128-pin tqfp and 84-pin mlcc only) pin name pin # 128-pin tqfp pin # 84-pin mlcc pin description functional description gtx_clk 121 77 transmit clock the mac drives this 125 mhz clock signal that is held low during autonegotiation or when operating in modes other than 1000base-t. tx_er 124 78 transmit error the mac drives this signal high to indicate a transmit coding error. tx_en 125 79 transmit enable the mac drives this signal high to indicate that data is available on the transmit data bus. txd[7:0] 7, 6, 5, 4, 3, 128, 127, 126 3, 2, 1, 84, 83, 82, 81, 80 transmit data bits 7?0 the mac transmits data synchronized with gtx_clk to the et1011 for transmission on the media dependent (transformer) interface. rx_clk 113 72 receive clock the et1011 generates a 125 mhz clock to synchronize receive data. rx_er 110 70 receive error the et1011 drives rx_er to indicate that an error was detected in the frame that was received and is being transmitted to the mac. rx_dv 109 69 receive data valid the et1011 drives rx_dv to indicate that it is sending recovered and decoded data to the mac. rxd[7:0] 97, 98, 99, 100, 105, 106, 107, 108 59, 60. 61, 62, 65, 66, 67, 68 receive data the et1011 transmits data that is synchronized with rx_clk to the mac. crs 116 74 carrier sense the carrier sense signal (crs) of the mac interface is asserted by the et1011 whenever the receive medium is nonidle. in half-duplex mode, crs may also be asserted when the transmit medium is nonidle. the crs may be enabled on transmit in half- duplex mode by writing to the phy configuration register, address 22, bit 15. col 115 73 collision detect in 10base-t, 100base-tx, and 1000 base-t half-duplex modes, col is asserted when both transmit and receive media are nonidle.
agere systems inc. 23 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) reduced gigabit media independent interface (rgmii) the rgmii interface is fully compliant with the rgmii rev. 1.3 specification. th e rgmii interface mode is selected by setting the hardware configuration pins mac_if_sel[2:0] = 100 (trace delay) or 110 (dll delay). figure 11. rgmii mac-phy signals txc txd[3:0] tx_ctl rxc rxd[3:0] rx_ctl mac phy table 4. rgmii signal description (1000base-t mode) 1. reference the gmii interface for description of the foll owing parameters: tx_en, tx_er, rx_dv, rx_en, and rx_er. pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description txc 121 77 63 transmit clock the mac drives this 125 mhz clock signal that is held low during autonegotiation or when operating in modes other than 1000base-t. to obtain the 1 gigabit transmission rate, the mac uses both the positive and negative clock transitions. txd[3:0] 3, 128, 127, 126 83, 82, 81, 80 68, 67, 66, 65 transmit data bits the mac transmits data synchronized with txc to the et1011 for transmission on the media dependent (transformer) interface. the mac transmits bits 3:0 on a positive transition of txc and bits 7:4 on a negative transition of txc. tx_ctl 125 79 64 transmit control the mac transmits control signals across this line (tx_er and tx_en). the mac transmits tx_en 1 on a positive transition of txc and tx_en and tx_er 1 on the negative transition of txc. rxc 113 72 60 receive clock the et1011 generates a 125 mhz clock to syn- chronize receive data. to obtain the 1 gigabit transmission rate, the et1011 uses both the posi- tive and negative clock transitions. rxd[3:0] 105, 106, 107, 108 65, 66, 67, 68 54, 55, 56, 57 receive data the et1011 transmits data that is synchronized with rx_clk to the mac. the et1011 transmits bits 3:0 on a positive transition of rxc and bits 7:4 on the negative transition of rxc. rx_ctl 109 69 58 receive control the et1011 transmits control signals across this line (rx_er and rx_en). the et1011 transmits rx_dv 1 on a positive transition of rxc and rx_en 1 and rx_er 1 on the negative transition of txc.
24 24 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) media independent interface (mii) (128-pin tqfp only) the mii is fully compliant with ieee 802.3 clause 22. the mii interface mode is selected by setting the hard- ware configuration pins mac_if_sel[2:0] = 000. in 100base-tx and 10base-t mode, the rxd[7:4] pins are driven low by the et1011 and the txd[7:4] pins are ignored. they should not be left floating but should be set either high or low. in the mii interface mode, the gtx_clk pin may be held low. an alternative to the standard mii is provided when operating in 10base-t or 100base-tx mode by setting hardware configuration pins mac_if_sel[2:0] = 010. in th is alternative interface, the mac provides a reference clock at 2.5 mhz or 25 mhz at the gtx_clk pin. the et1011 then uses a fifo to resynchronize data presented synchronously with this reference clock. figure 12. mii signals mac phy col rx_er rx_dv rxd[3:0] crs tx_clk tx_er tx_en txd[3:0] rx_clk table 5. mii interface (100base-tx and 10base -t) (128-pin tqfp an d 84-pin mlcc only)) pin name pin # 128-pin tqfp pin # 84-pin mlcc pin description functional description tx_clk 118 75 transmit clock in 100base-tx mode, the et1011 generates 25 mhz reference clocks and in 10base-t mode prov ides 2.5 mhz reference clocks. mac_if_sel[2:0] = 000?this is default behavior. gtx_clk 121 77 alternate transmit clock in 100base-tx mode, the mac generates the 25 mhz reference clock and in 10base-t mode provides a 2.5 mhz reference clock. mac_if_sel[2:0] = 010. tx_er 124 78 transmit error the mac drives this signal high to indicate a transmit coding error. tx_en 125 79 transmit enable the mac drives this signal high to indicate that data is available on the transmit data bus. txd[3:0] 3, 128, 127, 126 83, 82, 81, 80 transmit data bits the mac transmits data synchronized with tx_clk to the et1011 for transmission on the media-dependent (transformer) interface. rx_clk 113 72 receive clock in 100base-tx mode, the et1011 generates 25 mhz reference clocks and in 10base-t mode prov ides 2.5 mhz reference clocks. rx_er 110 70 receive error the et1011 drives rx_er to indicate that an error was detected in the frame that was received and is being transmitted to the mac. rx_dv 109 69 receive data valid the et1011 drives rx_dv to indicate that it is sending recovered and decoded data to the mac. rxd[3:0] 105, 106, 107, 108 65, 66, 67, 68 receive data bits the et1011 transmits data synchronized with rx_clk to the mac. crs 116 74 carrier sense the carrier sense signal (crs) of the mac interface is asserted by the et1011 whenever the receive medium is nonidle. in half- duplex mode, crs may also be asserted when the transmit medium is non-idle. the crs may be enabled on transmit in half- duplex mode by writing to the ph y configuration register, address 22, bit 15. col 115 73 collision detect in 10base-t, 100base-tx, and 1000base-t half-duplex modes, col is asserted when both trans mit and receive media are noni- dle.
agere systems inc. 25 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) ten-bit interface (tbi) (128-pin tqfp only) the tbi is fully compliant with ieee 802.3 clause 36. it may be used as an alternative to the gmii in 1000base-t mode. the tbi mode is selected by set- ting the hardware configuration pins mac_if_sel[2:0] = 001. figure 13. ten-bit interface mac phy pma_rx_clk[1] rxd[9] rxd[8] rxd[7:0] pma_tx_clk txd[9] txd[8] txd[7:0] pma_rx_clk col rxd[7:0] rx_dv rx_clk rx_er gtx-clk tx_en tx_er txd[7:0] comma crs table 6. ten-bit interface (1000base-t) (128-pin tqfp and 84-pin mlcc only) pin name pin # 128-pin tqfp pin # 84-pin mlcc pin description functional description pma_tx _clk 121 77 tbi transmit clock the mac drives this 125 mhz clock signal and should be held low during autonegotiation or when operating in modes other than 1000base-t. txd[9:0] 124, 125, 7, 6, 5, 4, 3, 128, 127, 126 78, 79, 3, 2, 1, 84, 83, 82, 81, 80 transmit data bits the mac transmits data synchronized with pma_tx_clk to the et1011 for transmission on the media dependent (transformer) inter- face. pma_rx _clk[0] 113 72 receive clock the et1011 generates a 62.5 mhz clock to synchronize receive data for the odd code group. this signal is 180 degrees out of phase from pma_rx_clk[1]. rxd[9:0] 110, 109, 97, 98, 99, 100, 105, 106, 107, 108 70, 69, 59, 60, 61, 62, 65, 66, 67, 68 receive data bits the et1011 transmits data that is synchro- nized with pma_ rx_clk[0] to the mac. pma_rx _clk[1] 115 73 receive clock the et1011 generates a 62.5 mhz clock to synchronize receive data for the even code group. this signal is 180 degrees out of phase from pma_rx_clk[0]. comma 116 74 comma signal this signal indicates that comma has been detected.
26 26 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) reduced ten-bit interface (rtbi) the rtbi is fully compliant with rgmii rev 1.3 specifi- cation. the rtbi mode is selected by setting the hard- ware configuration pins mac_if_sel[2:0] = 101 (trace delay) or 111 (dll delay). figure 14. reduced ten-bit interface txc txd[4:0] rxc rxd[4:0] mac phy tx_ctl rxd[3:0] txd[3:0] rx_ctl table 7. rtbi signal description (1000base-t mode) pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description txc 121 77 63 transmit clock the mac drives this 125 mhz clock signal that is held low during autonegotiation or when oper- ating in modes other than 1000base-t. txd[3:0] 3, 128, 127, 126 83, 82, 81, 80 68, 67, 66, 65 transmit data bits the mac transmits data synchronized with txc to the et1011 for tran smission on the media dependent (transformer) interface. the mac transmits bits 3:0 on a positive transition of txc and bits 8:5 on a negative transition of txc. tx_ctl 125 79 64 transmit control the mac transmits bit 5 and bit 10 synchro- nized with txc to the et1011 for transmission on the media-dependent (transformer) interface. the mac transmits bit 5 on a positive transition of txc and bit 10 on the negative transition of txc. rxc 113 72 60 receive clock the et1011 generates a 125 mhz clock to syn- chronize receive data. rxd[3:0] 105, 106, 107, 108 65, 66, 67, 68 54, 55, 56, 57 receive data the et1011 transmits data that is synchronized with rxc to the mac. the et1011 transmits bits 3:0 on a positive transition of rxc and bits 8:5 on the negative transition of rxc. rx_ctl 109 69 58 receive control the et1011 transmits bit 5 and bit 10 synchro- nized with rxc to the mac. the et1011 trans- mits bit 5 on a positive transition of rxc and bit 10 on the negative transition of rxc.
agere systems inc. 27 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) management interface serial management interface the mii management interface (mi) provides a simple, two-wire serial interface between the mac and the phy to allow access to control and status information in the internal registers of the et1011. the interface is compliant with ieee 802.3 clause 22 and is compatible with the clause 45.3, enabling the two syste ms to co-exist on the same mdio bus. management frame structure frames transmitted on the mi have the following structure. table 8. management frame structure q pre (preamble): at the beginning of each transaction, t he mac may send a sequence of 32 contiguous logic one bits on mdio with 32 corresponding cycles on mdc to provide the phy with a pattern that it can use to establish synchronization. the et1011 supports mf preamble suppression, and thus the mac may initiate man- agement frames with the st (start of frame) pattern. q st (start of frame): the start of frame is indicated by a <01> pattern. this pattern ensures transitions from the default logic one line state to zero and back to one. when a clause 45 start of frame <00> is received, the frame is ignored. q op (operation code): the operation code for a read trans action is <10>, while the operation code for a write transaction is <01>. q phyad (phy address): the phy address is 5 bits. the firs t phy address bit transmitted and received is the msb of the address. only the phy that is addressed will respond to the mi operation. q regad (register address): the register address is 5 bits. th e first register address bit transmitted and received is the msb of the address. q ta (turnaround): the turnaround time is a 2-bit time spacin g between the register addres s field and the data field of a management frame to avoid contention during a read transaction. for a read transaction, the phy remains in a high-impedance state for the first bit time of the tu rnaround and drives a zero bit during the second bit time of the turnaround. during a write transaction, the phy expec ts a one for the first bit time of the turnaround and a zero for the second bit time of the turnaround. q data (data): the data field is 16 bits. the first data bit tran smitted and received is the msb of the register being addressed. q idle (idle condition): the idle condition on mdio is a high-impedance state, and the et1011 internal pull-up resistor will pull the md io line to logic one. pre st op phyad regad ta data idle read 1 . . . 1 01 10 aaaaa rrrrr zo d . . . d z write 1 . . . 1 01 01 aaaaa rrrrr 10 d . . . d z
28 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) table 9. management interface 1. phyad description applies to the 128-tqfp only . for the 68-mlcc, the valid range will be 0?15. management interrupt the et1011 is capable of generating hardware interrupts on pin mdint_n in response to a variety of user-select- able conditions. mdint_n is an open-drain, active-low signal that can be wire-ored with several other et1011 devices. a single 2.2 k ? pull-up resistor is recommended for this wire-or configuration. when an interrupt occurs, the system can poll the status of the interrupt status register on each device to deter- mine the origin of the interrupt. there are nine condit ions that can be selected to generate an interrupt: the et1011 is configured to generate an interrupt based on any of these conditions by use of the interrupt mask register (mii register 24). by setting the corresponding bi t in the interrupt mask regist er for the desired condition, the et1011 will generate the de sired interrupt. the et1011 can be polled on the status of an activated interrupt condition by accessing mii register interrupt status register (mii register 25). if this condition has occurred, the cor- responding bit in the in terrupt status register will be se t. the interrupt status register is self-clearing on a read oper- ation. pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description phyad [4:0] 67, 68, 69, 70, 71 40, 41, 42, 43, 44 34, 35, 36, 37 (phyad [3:0]) phy address the physical address of the et1011 is configured at reset by the current state of the phyad[4:0] pins. once these pins have been latched in at reset, the et1011 is accessible via the management interface at the config- ured address. the default address is set to 1 by internal pull up/downs. these may be overridden by external pull-up/downs. the valid range is 0 to 31 1 . mdc 91 55 48 management interface clock the management data clock (mdc) is a reference for the data signal and is generated by the mac. it should be turned off when the mi is not being used. this pin has an internal pull-down resistor. mdc is nominally 2.5 mhz, and can work up to a maximum of 12.5 mhz. mdio 90 54 47 management data i/o the management data input/output (mdio) is a bidirec- tional data signal between the mac and one or more phys. mdio is a 3-state pin that allows either the mac or the selected phy to drive this signal. this pin has an internal pull-up resistor. an external pull-up resistor should also be used, the exact value depending on the number of phys sharing the mdio signal. data signals written by the mac are sampled by the phy synchro- nously with respect to the m dc. data signals written by the phy are generated synchronously with respect to the mdc. this pin requires an external pull-up (1 k ? to 10 k ? ). mdint_n 89 53 46 management interface interrupt this pin is active-low and indicates an unmasked man- agement interrupt. this pin requires an external pull-up resistor (1 k ? to 4.7 k ? ). pin is open drain. q autonegotiation status change q link status change q local/remote rx status change q autonegotiation page received q crc errors q automatic speed downshift occurred q fifo overflow/underflow q full error counter q mdio synchronization lost
agere systems inc. 29 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) configuration interface the hardware configuration pins listed in table 13 initialize the et1011 at poweron and reset. the configuration is latched during initialization and stored. these pins set th e default value of their corresponding mii register bits. some configuration inputs are shared with led pins. the hard ware configuration and led pins are read on initial powerup of the et1011, during a hardware reset and during recovery from hardware powerdown. the logic value at the pin is sensed and latched. after reset_n has been deasserted (raised high), the shared config uration pins become outputs that are used to drive leds 1 . note : the 68-mlcc, unlike its 128-tqfp counterpart, offers comparatively limited hardware configuration capa- bilities. it only has pause, spee d_1000, sys_clk_en_n, and lped_en_ n configuration pins. the other configuration inputs take on the default value at reset and can be changed via the mi registers. autonegotiation: speed and duplex selection the et1011 supports 10base-t, 100base-tx, and 1000base-t modes in both full and half duplex. for the pur- pose of autonegotiation, the ieee defines a technology as a combination of speed and duplex capability. the phy can be configured to advertise a subset of the available technologies as shown in table 10. once autonegotiation is completed, an attempt is made to bring up a link with the highest common denominator technology. table 10. autonegotiation modes autonegotiation can be disabled and the technology forced by writing to the control register (mi register address 0, bits 12). this causes the phy to transmit and receive in accordance with the selected technology irrespective of the capability of the link partner. disabl ing autonegotiation is not recommended. 1. for details on sharing led and configur ation pins, refer to the application note, truephy et1011 gigabit ethernet phy design and layout guide . sp_1000 sp_100 sp_10 duplex autonegotiation mode 0 0 1 0 advertise only 10base-t, half duplex. 0 0 1 1 advertise only 10base-t, full duplex. 0 1 0 0 advertise only 100base-tx, half duplex. 0 1 0 1 advertise only 100base-tx, full duplex. 1 0 0 0 advertise only 1000base-t, half duplex. 1 0 0 1 advertise only 1000base-t, full duplex. 0 1 1 0 advertise 10base-t and 100base-tx, half duplex. 0 1 1 1 advertise 10base-t and 100base-tx, full duplex. 1 0 1 0 advertise 10base-t and 1000base-t, half duplex. 1 0 1 1 advertise 10base-t and 1000base-t, full duplex. 1 1 0 0 advertise 100base-tx and 1000base-t, half duplex. 1 1 0 1 advertise 100base-tx and 1000base-t, full duplex. 1 1 1 0 advertise all capabilities, half duplex. 1 1 1 1 advertise all capabilities, full duplex.
30 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) autonegotiation: master/slave configuration a phy can advertise a preference for ma ster or slave. the hardware configuration pin mas_cfg sets the prefer- ence as shown in table 11. if both phys advertise the same master/slave preference , the master/slave configura- tion is resolved during autonegotiation as described in the ieee standards. table 11 . master/slave preference the phy can be manually configured for master or slave by writing to the 1000base-t control register (mi register address 9, bits 12 and 11). if both phys are manually c onfigured to the same master/slave setting, a 1000base-t link cannot be established. manual master /slave configuration is not recommended. mas_cfg autonegegotiation master/slave mode 0 autonegotiation, advert ise slave preference. 1 autonegotiation, advert ise master preference.
agere systems inc. 31 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) autonegotiation: mdi/mdi-x configuration the phy can be configured to automatically detect mdi/mdi -x configuration, or the mdi/mdi-x configuration can be forced as shown in table 12. table 12. mdi/mdi-x configuration table 13. configuration signals auto_mdi_en mdi_sel mdi/m di-x configuration 1 x automatic mdi/mdi-x detection. 0 0 mdi configuration (nic/dte). 0 1 mdi-x configuration (switch). pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description speed_1000 82 49 42 speed 1000 the speed configuration pins set the default advertised speed. the assertion of each input enables advertisement of the corresponding speed to the remote end. speed_1000 ? advertise 1000base-t speed_100 ? advertise 100base-tx speed_10 ? advertise 10base-t the default is to advertise all three speeds. speed_100 83 ? ? speed 100 speed_10 84 ? ? speed 10 duplex 75 ? ? duplex duplex selects the duplex mode to be advertised (half or both half and full). 0 = advertise half duplex. 1 = advertise both half and full duplex (default). mas_cfg 86 ? ? master slave configura- tion this input determines the master/slave preference. 0 = advertise a preferenc e to operate as slave (default). 1 = advertise a preference to operate as master. pause 85 50 43 pause this input sets the pause mode. if pause is asserted, full-duplex pause and asymmet- ric pause operation are advertised. 0 = don't advertise pause (default). 1 = advertise full-duplex pa use and asymmetric pause.
32 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) table 13. configuration signals (continued) 1. in the 68-mlcc, mac_if_sel 2 (=1) will be set internally. pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description auto_ mdi_ en 21 ? ? autoconfig- ure mdi/ mdi-x these inputs determine the mdi/mdi-x configuration. if auto_mdi_en is assert ed, automatic mdi/mdi-x detection is enabled and the mdi/mdi-x configuration is determined by the phy auto matically. the mdix_sel sig- nal is ignored. if auto_mdi_en is not assert ed, mdix_sel determines the mdi/mdi-x configuration. if mdix_sel is asserted, the mdi-x configuration is sele cted. if mdix_sel is not asserted, the mdi configuration is selected. autoconfigure mdi/mdi-x 0 = automatic mdi/mdi-x detection disabled. 1 = automatic mdi/mdi-x detection enabled (default). mdi/mdi-x selection 0 = mdi configuration (default). 1 = mdi-x configuration mode. mdix_sel 74 ? ? mdi/mdi-x selection mac_if_ sel[2:0] 20 19 18 18 17 16 ? 10 9 (mac_if_ sel[1:0] (see note 1.) mac inter- face mode this input selects the des ired mac interface mode. configure the mac during reset as follows: 000 = gmii/mii (128-tqfp default). 001 = tbi. 010 = gmii/mii (clocked by gtx_clk instead of tx_clk) 011 = reserved. 100 = rgmii (trace delay; 68-mlcc default). 101 = rtbi (trace delay). 110 = rgmii (dll delay). 111 = rtbi (dll delay). sys_clk_ en_n 15 13 6 sys_clk enable enables the system clock. if sys_clk_en_n is asserted when reset_n is low, sys_clk will be enabled and will continue to be gener- ated while reset_n is low. if sys_clk_en_n is not asserted when reset_n is low, then sys_clk is dis- abled. 0 = sys_clk enabled. 1 = sys_clk disabled (default). lped_en_ n 16 14 7 low power energy detection enable lped_en_n enables the low-power energy-detect (lped) mode when coma is asserted. when the phy is in lped mode, it can wake the mac/ controller (instead of magic packet ) by asserting the mdint_n pin to indicate the presence of cable energy. 0 = low-power energy-detect mode enable. 1 = low-power energy-detect mode disabled (default). pres 87 51 44 precision resistor connect a 1.0 k ? precision resistor to ground to set termi- nation for all digital i/o?s.
agere systems inc. 33 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) leds interface the et1011 is capable of sinking or sourcing current to drive leds. these leds are used to provide link status information to the user. the et1011 is capable of automati cally sensing the polarity of the leds. the device deter- mines the active sense of the led based upon the input that is latched during configuration. thus, if logic 1 is read, the device will drive the pin to ground to activate the led; otherwise, it will drive the pin to supply to activate the led. the leds can be programmed to stretch out events to either 28, 60, or 100 ms. this makes very short events more visible to the user. all leds can be programmed to be on, off, or blink instead of the default status function. this is useful for alternative function indication under host processor control: for example, a system error during power-on self-check. four of the leds (led_act, led_lnk 1 , led_100 and led_1000 1 ) can be programmed to indicate one of thirteen different status func tions instead of the default status function: the led drivers can be configured by use of le d control register 1 and led control register 2 (mii registers 27?28). 1. only led_lnk and led_1000 are available in the 68-pin mlcc. table 14. led q 1000base-t q transmit or receive activity q 100base-tx q full duplex q 10base-t q collision q 1000base-t (on) and 100base-tx (blink) q link established (on) and activity (blink) q link established q link established (on) and receive activity (blink) q transmit activity q full duplex (on) and collision (blink) q receive activity pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description led_1000 82 49 42 1000base-t led this led indi cates that the device is operating in 1000base-t mode. setting can be overridden. led_100 83 ? ? 100base-tx led this led indica tes that the device is operating in 100base-tx mode. setting can be overridden. led_10 84 ? ? 10base-t led this led indicates that the device is operating in 10base-t mode. setting can be overridden. led_dup 75 ? ? duplex led this led indicates that the device is operating in full-duplex mode. setting can be overridden. led_lnk 85 50 43 link established led this led indicates that th e link is established. set- ting can be overridden. led_col 86 ? ? collision led this led indica tes that both transmit and receive activity is occurring in half-duplex mode. setting can be overridden. led_act 74 ? ? transmit/receive activity led this led indicates that ther e is transmit or receive activity. setting can be overridden.
34 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) media-dependent interface: transformer interface table 15. transforme r interface signals pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description trd[0]+ trd[0]? 39 41 25 26 19 20 transmit and receive differ- ential pair 0 connect this signal pair through a transformer to the media-dependent interface. in 1000base-t mode, transmit and receive occur simultaneously at trd[0]. in 10base-t and 100base-tx modes, trd[0] are used to transmit when operating in the mdi configu- ration and to receive when operating in the mdi-x configuration. the phy automatically determines the appropriate mdi/mdi-x configuration. trd[1]+ trd[1]? 45 47 28 29 22 23 transmit/ receive differ- ential pair 1 connect this signal pair through a transformer to the media dependent interface. in 1000base-t mode, transmit and receive occurs simultaneously at trd[1]. in 10base-t and 100base-tx modes, trd[1] are used to receive when operating in the mdi configu- ration and to transmit when operating in the mdi-x configuration. the phy automatically determines the appropriate mdi/mdi-x configuration. trd[2]+ trd[2]? 54 56 34 35 28 29 transmit/ receive differ- ential pair 2 connect this signal pair through a transformer to the media-dependent interface. in 1000base-t mode, transmit and receive occurs simultaneously at trd[2]. in 10base-t and 100base-tx modes, trd[2] are unused. trd[3]+ trd[3]? 60 62 37 38 31 32 transmit/ receive differ- ential pair 3 connect this signal pair through a transformer to the media-dependent interface. in 1000base-t mode, transmit and receive occurs simultaneously at trd[3]. in 10base-t and 100base-tx modes, trd[3] are unused. rset 52 32 26 analog refer- ence resistor rset sets an absolute value reference current for the transmitter. connect this signal to analog ground through a pre- cision 6.34 k ? 1% resistor.
agere systems inc. 35 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) clocking and reset table 16. clocking and reset pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description clk_in 31 22 16 reference clock input connect this signal to a 25 mhz clock input (clk_in) or a 25 mhz 50 ppm tolerance crys- tal (xtal_1). xtal_1 31 22 16 reference crystal input xtal_2 32 23 17 reference crystal input connect this signal to a 25 mhz 50 ppm toler- ance crystal. float this signal if an external clock is used (clk_in). sys_clk 94 57 50 system clock use this signal to supply a 125 mhz clock to the mac. by default, the sys_clk ou tput is disabled. the sys_clk output can be enabled by asserting the sys_clk_en_n pin or via the management interface. reset_n 34 24 18 reset driv e reset_n low for 20 s to initiate a hard- ware reset. the et1011 completes all reset operations within 5 ms of this signal returning to a high state. the configuration pins and the physical address configuration are read during a hardware reset. coma 25 ? 12 hardware powerdown drive coma high to initiate a hardware power- down. the et1011 completes all reset opera- tions within 5 ms of this signal returning to a low state. all hardware functions are disabled during a hardware powerdown. the configuration pins and the physical address configuration are read during a hardware power- down.
36 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) jtag the et1011 has a standard ieee 1149.1 jtag test interface. the interf ace provides extensive test and diagnos- tics capability. it contains internal ci rcuitry that allows the devi ce to be controlled through the jtag port to provide on-chip, in-circuit emulation. the jtag interface is a bidirectional serial interface with its own reset strobe (trst_n). the reset strobe can be used independently to reset the jtag state machine but must be used during a power-on reset (see reset timing on page 78). table 17. jtag test interface regulator control the et1011 has two on-chip regulator controllers. this a llows the device to be powered from a single supply, either 3.3 v or 2.5 v. the on-chip regula tor control circuits provide output cont rol voltages that can be used to con- trol two external transistors and thus provide regulated 1.0 v and 2.5 v supplies. pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description tdi 16 14 7 test data input this signal is the jtag serial input. all instructions and scanned data are input us ing this pin. this pin has an internal pull-up resistor. tdo 17 15 8 test data output this signal is the jtag serial output. scanned data and status bits are output using this pin.this pin has an internal pull-up resistor. tck 10 5 2 test clock this signal is the jtag serial shift clock. it clocks all of the data that passes through the port on tdi and tdo. this pin has an internal pull-up resistor. tms 15 13 6 test mode select this signal is the jtag test mode control. this pin has an internal pull-up resistor. trst_n 14 12 5 test reset (jtag reset) this signal is active lo w and causes the jtag tap controller to enter the reset state. this pin has an internal pull-down resistor. table 18. regulator control interface pin name pin # 128-pin tqfp pin # 84-pin mlcc pin # 68-pin mlcc pin description functional description ctrl_1v0 79 47 40 regulator control for 1.0 v this is the regulator output control voltage for the 1.0 v supply. it is used to control an external transistor and thus provide a regulated 1.0 v supply. ctrl_2v5 78 46 39 regulator control for 2.5 v this is the regulator output control voltage for the 2.5 v supply. it is used to control an external transistor and thus provide a regulated 2.5 v supply.
agere systems inc. 37 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 hardware interfaces (continued) regulator control (continued) the et1011 digital and analog core operates at 1.0 v. th e analog i/o operates at 2.5 v. the digital i/o can operate at either 3.3 v or 2.5 v. the gmii interface operates at 3.3 v and the rgmii interfac e operates at 2.5 v. the on- chip regulator control allows the device to be operated fr om a wide variety of external supply combinations. when more than one external supply is available, one or both of the regulator control circuits may be left unused. table 19 lists example combinations of available extern al supplies and shows how the on-chip regulator control may be used to provide the required supplies. 1. even if the regulator controls are not connected, vdd_reg must be powered. power, ground, and no connect table 20. power, ground, and no connect 1. for the 84-pin and 68-pin mlcc, all avss and dvss pins share a common ground pin (exposed pad) in the center of the device. table 19. supply voltage combinations available external supplies avddl dvdd avddh vdd_reg 1 description 3.3 v only 1.0 1.0 2.5 3.3 digital i/o can be either 3.3 v or 2.5 v. regulator control is used to provide 1.0 v and 2.5 v. 2.5 v only 1.0 1.0 2.5 2.5 digital i/o is 2.5 v. regulator control is used to provide 1.0 v. 3.3 v and 1.0 v 1.0 1.0 2.5 3.3 digital i/o can be either 3.3 v or 2.5 v. regulator control is used to provide 2.5 v. 2.5 v and 1.0 v 1.0 1.0 2.5 2.5 digital i/o is 2.5 v. regulator controls are not connected. 3.3 v and 2.5 v 1.0 1.0 2.5 3.3 digital i/o can be either 3.3 v or 2.5 v. regulator control is used to provide 1.0 v. 3.3 v, 2.5 v, and 1.0 v 1.0 1.0 2.5 3.3 or 2.5 digital i/o can be either 3.3 v or 2.5 v. regulator controls are not connected. pin name pin description functional description vdd_reg v dd regulator 2.5 v or 3.3 v supply. dvddio v dd digital i/o 3.3 v or 2.5 v supply. dvdd v dd digital core 1.0 v supply. dvss v ss digital ground 1 . avddh v dd analog power 2.5 v. avddl v dd analog power 1.0 v. avss v ss analog ground 1 . nc no connect reserved?do not connect.
38 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 cable diagnostics the et1011 has on-chip cable diagnostics. the cable analysi s uses two distinct method s for evaluating the cable: link analysis and time domain reflectometry (tdr) analysis . this analysis can be used to detect cable impairments that may be preventing a gigabit link or affecting performance. when there is a link active, the link anal ysis can detect cable length, link qualit y, pair skew, pair swaps (mdi/mdi-x configuration), and polarity reversal. when there is no link, tdr can detect cable faults (open circuit, short circuit), distance to the fault, pair fault is on, cable length, pair skew, and excessive crosstalk. table 21 summarizes the specifications of the cable diagnostic functions. 1. pair swaps on c and d as well as pairs a and b are reported. 2. polarity reversal in 100base-tx is not detect ed because mlt-3 signaling is polarity insensitive. 3. if the magnitude of the peak reflection is greater than 15% of an open circuit . table 21. cable diagnostic functions feature description 10 100 1000 term unterm analysis detection of cable fault on any pair cable open ? ? ? 33 line probing cable short ? ? ? 33 indicate distance to fault ???2 m2 m pair swaps 333 1 ? ? link analysis detect polarity reversal ? 3 ? 2 3 ? ? link analysis good cable with link indicate length ? 5 m 5 m ? ? link analysis good cable without link indicate length ? ? ? 5 m 3 2 m line probing pair skew with link detect excessive, >50 ns ?? 3 ? ? link analysis pair skew without link detect excessive, >50 ns ??? 3 3 3 line probing excessive crosstalk cable quality or split pairs ??? 33 line probing
agere systems inc. 39 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description register address map table 22. register address map table 23. register type definition address description 0 control register. 1 status register. 2 phy identifier register 1. 3 phy identifier register 2. 4 autonegotiation advertisement register. 5 autonegotiation link pa rtner ability register. 6 autonegotiation expansion register. 7 autonegotiation next page transmit register. 8 link partner next page register. 9 1000base-t control register. 10 1000base-t status register. 11?14 reserved. 15 extended status register. 16?17 reserved. 18 phy control register 2. 19 loopback control register. 20 reserved. 21 register management (mi) control register. 22 phy configuration register. 23 phy control register. 24 interrupt mask register. 25 interrupt status register. 26 phy status register. 27 led control register 1. 28 led control register 2. 29-31 reserved. type description ll latching low. lh latching high. r/w read write. register can be read or written. ro read only. register is read only. writes to reg- ister are ignored. sc self-clearing. register is self-clearing; if a one is written, the register will automatically clear to zero after the func tion is completed.
40 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings table 24. control register?address 0 1. the reset bit is automatically cleared upon completion of the reset sequence. this bit is set to 1 during reset. 2. this is the master enable for digital and analog loopback as de fined by the standard. the exact type of loopback is determine d by the loopback control register (address 19). 3. the speed selection address 0 bits 13 and 6 may be used to conf igure the link manually. setting these bits has no effect unle ss address 0 bit 12 is clear. the speed bits are set by the speed_10, speed_100, and speed_1000 pins at reset. 4. when this bit is cleared, the link configuration is determined manually. 5. setting this bit isolates the phy fr om the mii, gmii, or rgmii interfaces. 6. this bit may be used to configure the link manually. setting this bit has no effect unless addr ess 0 bit 12 is clear. duplex is set on reset by the duplex pin. 7. enables ieee 22.2.4.1.9 collision test. control register bit name description type default notes 15 reset 1 = phy reset. 0 = normal operation. r/w sc 01 14 loopback 1 = enable loopback. 0 = disable loopback. r/w 0 2 13 speed selection (lsb) bit 6,13. 11 = reserved. 10 = 1000 mbits/s. 01 = 100 mbits/s. 00 = 10 mbits/s. r/w speed_1000 speed_100 speed_10 3 12 autonegotiation enable 1 = enable autonegotiation process. 0 = disable autonegotiation process. r/w 1 4 11 powerdown 1 = powerdown. 0 = normal operation. r/w 0 ? 10 isolate 1 = isolate phy from mii. 0 = normal operation. r/w 0 5 9 restart autonegoti- ation 1 = restart autonegotiation process. 0 = normal operation. r/w sc 0? 8 duplex mode 1 = full duplex. 0 = half duplex. r/w duplex 6 7 collision test 1 = enable collision test. 0 = disable collision test. r/w 0 7 6 speed selection (msb) see bit 13. r/w see bit 13 3 5:0 reserved ? ro 0 ?
agere systems inc. 41 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 25. status register?address 1 1. the et1011 does not support 100base-t4 or 100base-t2, ther efore, these register bits will always be set to zero. 2. these bits receive values from the speed_10, speed_100, speed_1000, and duplex pins during reset as follows: 3. upon completion of autonegotiation, this bit becomes set. 4. this bit indicates that a remote fault has been detected. once set, it remains set until it is cleared by reading register 1 via the management interface or by phy reset. 5. this bit indicates that a valid link has been established. once cleared due to link failure, this bit will remain cleared unt il register 1 is read via the management interface. 6. indicates that the phy provides an extended set of capabili ties that may be accessed through the extended register set. for a phy that incorporates a gmii/rgmii, the extended regist er set consists of all management regi sters except registers 0, 1, and 15. status register bit name description type default notes 15 100base-t4 0 = not 100base-t4 capable. ro 0 1 14 100base-x full duplex 1 = 100base-x full-duplex capable. 0 = not 100base-x full-duplex capable. ro speed_100 and duplex 2 13 100base-x half duplex 1 = 100base-x half-duplex capable. 0 = not 100base-x half-duplex capable. ro speed_100 2 12 10base-t full-duplex 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. ro speed_10 and duplex 2 11 10base-t half-duplex 1 = 10 base-t half-duplex capable. 0 = not 10base-t half-duplex capable. ro speed_10 2 10 100base-t2 full-duplex 0 = not 100base-t2 full-duplex capable. ro 0 ? 9 100base-t2 half-duple x 0 = not 100base-t2 half-duplex capable. ro 0 ? 8 extended status 1 = extended stat us information in register 0fh. ro 1 ? 7 reserved ? ro ? ? 6 mf preamble suppression 1 = preamble suppressed management frames accepted. ro 1 ? 5 autonegotiation complete 1 = autonegotiation process complete. 0 = autonegotiation process not complete. ro 0 3 4 remote fault 1 = remote fault detected. 0 = no remote fault detected. ro lh 04 3 autonegotiation ability 1 = autonegotiation capable. 0 = not autonegotiation capable. ro 1 ? 2 link status 1 = link is up. 0 = link is down. ro ll 05 1 jabber detect 1 = jabber condition detected. 0 = no jabber condition detected. ro lh 0? 0 extended capability 1 = extend ed register capabilities. ro 1 6 register bit configuration pin combination 14 speed_100 and duplex 13 speed_100 12 speed_10 and duplex 11 speed_10
42 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 26. phy identifier register 1?address 2 table 27. phy identifier register 2?address 3 1. agere?s oui is 00-05-3d. phy identifier register 1 bit name description type default notes 15:0 phy identifier bits 3:18 organizationally unique identifier (oui), bits 3:18. ro 0x0282 1 phy identifier register 2 bit name description type default notes 15:10 phy identifier bits 19:24 organizationally unique identifier (oui), bits 19:24. ro 111100 1 9:4 model number model number = 1. ro 000001 ? 3:0 revision number revision number = 2. ro 0010 ?
agere systems inc. 43 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 28. autonegotiation advertisement register?address 4 1. value read from pause on reset. 2. the et1011 does not support 100base-t4, so the default value of this register bit is zero. 3. these bits receive values from the c onfiguration pins upon reset as follows: note: any write to this register prior to the completion of autonegotiation is followed by a restart of autonegotiation. also n ote that this register is not updated following autonegotiation. autonegotiation advertisement register 1 bit name description type default notes 15 next page 1 = advertise ne xt page ability supported. 0 = advertise next page ability not supported. r/w 0 ? 14 reserved ? ro 0 ? 13 remote fault 1 = advertise remote fault detected. 0 = advertise no remote fault detected. r/w 0 ? 12 reserved ? ro 0 ? 11 asymmetric pause 1 = advert ise asymmetric pause ability. 0 = advertise no asymmetric pause ability. r/w pause 1 10 pause capable 1 = capable of full-duplex pause operation. 0 = not capable of pause operation. r/w pause 1 9 100base-t4 capa- bility 1 = 100base-t4 capable. 0 = not 100base-t4 capable. r/w 0 2 8 100base-tx full- duplex capable 1 = 100base-tx full-duplex capable. 0 = not 100base-tx full-duplex capable. r/w speed_100 and duplex 3 7 100base-tx half- duplex capable 1 = 100base-tx half-duplex capable. 0 = not 100base-tx half-duplex capable. r/w speed_100 3 6 10base-t full- duplex capable 1 = 10base-t full-duplex capable. 0 = not 10base-t full-duplex capable. r/w speed_10 and duplex 3 5 10base-t half- duplex capable 1 = 10base-t half-duplex capable. 0 = not 10base-t half-duplex capable. r/w speed_10 3 4:0 selector field 00001 = ieee 802.3 csma/cd. r/w 00001 ? register bit configuration pin combination 8 speed_100 and duplex 7 speed_100 6 speed_10 and duplex 5 speed_10
44 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 29. autonegotiation link partner ability register?address 5 autonegotiation link partner ability register bit name description type default notes 15 next page 1 = link partner has next page ability. 0 = link partner does not have next page ability. ro 0 ? 14 acknowledge 1 = link partner has received link code word. 0 = link partner has not received link code word. ro 0 ? 13 remote fault 1 = link partner has detected remote fault. 0 = link partner has not detected remote fault. ro 0 ? 12 reserved ? ro 0 ? 11 asymmetric pause 1 = link partner desired asymmetric pause. 0 = link partner does not desire asymmetric pause. ro 0 ? 10 pause capable 1 = link partner capable of full-duplex pause operation. 0 = link partner is not capable of pause opera- tion. ro 0 ? 9 100base-t4 capability 1 = link partner is 100base-t4 capable. 0 = link partner is not 100base-t4 capable. ro 0 ? 8 100base-tx full- duplex capable 1 = link partner is 100base-tx full-duplex capa- ble. 0 = link partner is not 100base-tx full-duplex capable. ro 0 ? 7 100base-tx half- duplex capable 1 = link partner is 100base-tx half-duplex capa- ble. 0 = link partner is not 100base-tx half-duplex capable. ro 0 ? 6 10base-t full- duplex capable 1 = link partner is 10base-t full-duplex capable. 0 = link partner is not 10base-t full-duplex capa- ble. ro 0 ? 5 10base-t half- duplex capable 1 = link partner is 10base-t half-duplex capable. 0 = link partner is not 10base-t half-duplex capable. ro 0 ? 4:0 protocol selector field link partner protocol selector field. ro 0 ?
agere systems inc. 45 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 30. autonegotiation expansion register?address 6 table 31. autonegotiation next page transmit register?address 7 autonegotiation expansion register bit name description type default notes 15:5 reserved ? ro ? ? 4 parallel detection fault 1 = parallel link fault detected. 0 = parallel link fault not detected. ro lh 0? 3 link partner next page ability 1 = link partner has next page capability. 0 = link partner does not have next page capabil- ity. ro 0 ? 2next page capa- bility 1 = local device has next page capability. 0 = local device does not have next page capa- bility. ro lh 1? 1 page received 1 = new page has been received from link part- ner. 0 = new page has not been received. ro lh 0? 0 link partner auto- negotiation ability 1 = link partner has au tonegotiation capability. 0 = link partner does not have autonegotiation capability. ro 0 ? autonegotiation next page transmit register bit name description type default notes 15 next page 1 = additional next pages follow. 0 = sending last next page. r/w 0 ? 14 reserved ? ro 0 ? 13 message page 1 = formatted page. 0 = unformatted page. r/w 1 ? 12 acknowledge 2 1 = complies with message. 0 = cannot comply with message. r/w 0 ? 11 toggle 1 = previous value of transmitted link code word was logic zero. 0 = previous value of tr ansmitted link code word was logic one. ro 0 ? 10:0 message/ unformatted code field next page message code or unformatted data. r/w 1 ?
46 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 32. link partner next page register?address 8 link partner next page register bit name description type default notes 15 next page 1 = additional next pages follow. 0 = sending last next page. ro 0 ? 14 acknowledge 1 = acknowledge. 0 = no acknowledge. ro 0 ? 13 message page 1 = formatted page. 0 = unformatted page. r/w 0 ? 12 acknowledge 2 1 = complies with message. 0 = cannot comply with message. r/w 0 ? 11 toggle 1 = previous value of transmitted link code word was logic zero. 0 = previous value of transmitted link code word was logic one. ro 0 ? 10:0 message/ unformatted code field next page message code or unformatted data. r/w 0 ?
agere systems inc. 47 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 33. 1000 base-t control register?address 9 1. value read from mas_cfg pin at reset. setting this bit has no effect unless address 9 bit 12 is set. 2. value read from mas_cfg at reset. 3. value is a result of (speed_1000 and duplex) pins at reset. 4. value read from speed_1000 pin at reset. note: logically, bits 12:8 may be regarded as an extens ion of the technology ability field of register 4. 1000base-t control register bit name description type default notes 15:13 test mode 000 = normal mode. 001 = test mode 1?transmit waveform test. 010 = test mode 2?master transmit jitter test. 011 = test mode 3?slave transmit jitter test (slave mode). 100 = test mode 4?transmit distortion test. 101, 110, 111 = reserved. r/w 000 ? 12 master/slave configuration enable 1 = enable master/slave configuration. 0 = automatic master/s lave configuration. r/w 0 ? 11 master/slave configuration value 1 = configure phy as master. 0 = configure phy as slave. r/w mas_cfg 1 10 port type 1 = prefer multiport device (master). 0 = prefer single-port device (slave). r/w mas_cfg 2 9advertise 1000base-t full-duplex capability 1 = advertise 1000base-t full-duplex capability. 0 = advertise no 1000base-t full-duplex capability. r/w speed_1000 and duplex 3 8advertise 1000base-t half-duplex capability 1 = advertise 1000base-t half-duplex capability. 0 = advertise no 1000base-t half-duplex capability. r/w speed_1000 4 7:0 reserved ? ro 9.7:0 ?
48 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 34. 1000base-t status register?address 10 1. once set, this bit remains set until cleared by the following actions: q read of register 10 via the management interface. q reset. q completion of autonegotiation. q enable of autonegotiation. 2. this bit is not valid when bit 15 is set. 3. note that logically, bits 11:10 may be regarded as an extension of the technology abi lity field of register 5. 4. these bits contain a cumulative count of the errors detected when the receiver is receiving idles and both local and remote r eceiver status are ok. the count is held at 255 in the event of overflow and is reset to zero by reading register 10 via the management interf ace or by reset. 1000base-t status register bit name description type default notes 15 master/ slave configu- ration fault 1 = master/slave configuration fault detected. 0 = no master/slave configuration fault detected. ro, lh, sc 01 14 master/slave configuration resolution 1 = local phy resolved to master. 0 = local phy resolved to slave. ro 0 2 13 local receiver status 1 = local receiver okay. 0 = local receiver not okay. ro 0 ? 12 remote receiver status 1 = remote receiver okay. 0 = remote receiver not okay. ro 0 ? 11 link partner 1000base-t full-duplex capability 1 = link partner is capable of 1000base-t full duplex. 0 = link partner not 1000base-t full-duplex capable. ro 0 3 10 link partner 1000base-t half-duplex capability 1 = link partner is 1000base-t half-duplex capable. 0 = link partner not 1000base-t half-duplex capable. ro 0 3 9:8 reserved ? ro ? 7:0 idle error count msb of idle error count. ro 0 4
agere systems inc. 49 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description register functions/settings (continued) table 35. reserved registers?addresses 11?14 table 36. extended status register?address 15 1. value is a result of (speed_1000 and duplex) pins at reset. table 37. reserved registers?addresses 16?18 reserved registers bit name description type default notes 15:0 reserved ? ? ? ? extended status register bit name description type default notes 15 1000base-x full- duplex 0 = not 1000base-x full-duplex capable. ro 0 ? 14 1000base-x half- duplex 0 = not 1000base-x half-duplex capable. ro 0 ? 13 1000base-t full- duplex 1 = 1000base-t full-duplex capable. 0 = not 1000base-t full-duplex capable. ro 1 1 12 1000base-t half- duplex 1 = 1000base-t half-duplex capable. 0 = not 1000base-t half-duplex capable. ro 1 ? 11:0 reserved ? ro 0 ? reserved registers bit name description type default notes 15:0 reserved ? ? ? ?
50 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 38. loopback control register?address 19 1. replica loopback is not available in 10base-t. table 39. reserved registers?address 20 table 40. management interface (mi) control register?address 21 loopback control register bit name description type default notes 15 mii select 1 = mii loopback selected. 0 = mii loopback not selected. r/w 1 ? 14:13 reserved ? ? ? ? 12 all digital select 1 = all digital loopback selected. 0 = all digital loopback not selected. r/w 0 ? 11 replica select 1 = rep lica loopback selected. 0 = replica loopback not selected. r/w 0 1 10 line driver select 1 = line driver loopback selected. 0 = line driver loopback not selected. r/w 0 ? 9:0 reserved ? ? ? ? reserved registers bit name description type default notes 15:0 reserved ? ? ? ? management interface (mi) control register bit name description type default notes 15:3 reserved ? ? ? ? 2 ignore 10g frames 1 = management frames with st = <00> are ignored. 0 = management frames with st = <00> are treated as wrong frames r/w 1 ? 1 reserved ? ? ? ? 0 preamble sup- pression enable 1 = mi preamble is ignored. 0 = mi preamble is required. r/w 1 ?
agere systems inc. 51 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 41. phy configuration register?address 22 1. if automatic speed downshift is enabled and the phy fails to aut onegotiate at 1000base-t, the phy will fall back to attempt connection at 100base-tx and, subsequently, 10base-t. this cycle will repeat. if the link is broken at any speed, the phy will restart this p rocess by reat- tempting connection at the highest possible speed (e.g., 1000base-t). 2. value is read from inversion of sys_clk_en_n at reset. 3. for the 68-pin mlcc, only rgmii and rtbi modes/options are supported. phy configuration register bit name description type default notes 15 crs transmit enable 1 = enable crs on transmit in half-duplex mode. 0 = disable crs on transmit. r/w 0 ? 14 reserved ? ? ? ? 13:12 transmit fifo depth (1000base-t) 00 = 8. 01 = 16. 10 = 24. 11 = 32. r/w 01 ? 11:10 automatic speed downshift mode 00 = disable automatic speed downshift. 01 = 10base-t downshift enabled. 10 = 100base-tx downshift enabled. 11 = 100base-tx and 10base-t enabled. r/w 11 1 9 tbi detect select 1 = crs pin outputs comma detect. 0 = crs pin outputs link status detect r/w 0 ? 8 tbi rate select 1 = output 125 mhz clock on rx_clk while col is held low (full rate). 0 = output even/odd clocks on rx_clk/col r/w 0 ? 7 alternate next-page 1 = enables manual control of 1000base-t next pages only. 0 = normal operation of 1000base-t next page exchange r/w 0 ? 6 group mdio mode enable 1 = enable group mdio mode. 0 = disable group mdio mode. r/w 0 ? 5 transmit clock enable 1 = enable output of 1000base-t transmit clock (tx_clk pin). 0 = disable output. r/w 0 ? 4 system clock enable 1 = enable output of 125 mhz reference clock (sys_clk pin). 0 = disable output of 125 mhz reference clock. r/w sys_clk_en_n 2 3 reserved ? ? ? ? 2:0 mac interface mode select 000 = gmii/mii 001 = tbi 010 = gmii/mii clocked by gtx_clk instead of tx_clk 011 = reserved. 100 = rgmii (trace delay). 101 = rtbi (trace delay). 110 = rgmii (dll delay). 111 = rtbi (dll delay). r/w mac_if_sel [2:0] 3
52 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 42. phy control register?address 23 1. this bit allows independent control over txc and rxc dll delay. settings are shown below. phy control register bit name description type default notes 15:13 reserved ? ? ? ? 12:11 automatic speed downshift attempts before downshift 00 = 1. 01 = 2. 10 = 3. 11 = 4. r/w 01 ? 10:7 reserved ? ? ? ? 6 alternative rgmii txc dll delay 1 = txc dll delay in rgmii mode is opposite of rxc. 0 = txc dll delay in rgmii mode is same as rxc. r/w 0 1 5 jabber (10base-t) 1 = disable jabber. 0 = normal operation. r/w 0 ? 4sqe (10base-t) 1 = enable heartbeat. 0 = disable heartbeat. r/w 0 ? 3 tp_loopback (10base-t) 1 = disable tp loopback during half-duplex. 0 = normal operation. r/w 1 ? 2 preamble gener- ation enable 1 = enable preamble generation for 10base-t. 0 = disable preamble generation for 10base-t. r/w 1 ? 1 reserved ? ? ? ? 0 force interrupt 1 = assert mdint_n pin. 0 = deassert mdint_n pin. r/w 0 ? rgmii mode delay description 22.2:0 23.6 txc rxc 10x 0 0 ns 0 ns rgmii (trace delay). 11x 0 2 ns 2 ns rgmii (txc and rxc dll delay). 10x 1 2 ns 0 ns rgmii (txc dll delay). 11x 1 0 ns 2 ns rgmii (rxc dll delay).
agere systems inc. 53 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 43. interrupt mask register?address 24 1. mdint_n is asserted (active low) if mii interrupt pending = 1. interrupt mask register bit name description type default notes 15:10 reserved ? ? ? ? 9 mdio sync lost 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 8 autonegotiation status change 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 7 crc errors 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 6next page received 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 5 error counter full 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 4 fifo overflow/ underflow 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 3 receive status change 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 2 link status change 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 1 automatic speed downshift 1 = interrupt enabled. 0 = interrupt disabled. r/w 0 ? 0 mdint_n enable 1 = mdint_n enabled 1 . 0 = mdint_n disabled. r/w 0 ?
54 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 44. interrupt status register?address 25 1. if the management frame preamble is suppressed (mf preamble suppre ssion, register 0, bit 6), it is possible for the phy to l ose synchroniza- tion if there is a glitch at the interfac e. the phy can recover if a single frame with a preamble is sent to the phy. the mdio sync lost interrupt can be used to detect loss of synchronization and thus enable recovery. 2. an event has occurred and the correspondi ng interrupt mask bit is enabled (set = 1). interrupt status register bit name description type default notes 15:10 reserved ? ? ? ? 9 mdio sync lost 1 = event has occurred. 0 = event has not occurred. ro sc 01 8 autonegotiation status change 1 = event has occurred. 0 = event has not occurred. ro sc 0? 7 crc errors 1 = event has occurred. 0 = event has not occurred. ro sc 0? 6 next page received 1 = event has occurred. 0 = event has not occurred. ro sc 0? 5 error counter full 1 = event has occurred. 0 = event has not occurred. ro sc 0? 4 fifo overflow/ underflow 1 = event has occurred. 0 = event has not occurred. ro sc 0? 3 receive status change 1 = event has occurred. 0 = event has not occurred. ro sc 0? 2 link status change 1 = event has occurred. 0 = event has not occurred. ro sc 0? 1 automatic speed downshift 1 = event has occurred. 0 = event has not occurred. ro sc 0? 0 mii interrupt pending 1 = interrupt pending. 0 = no interrupt pending. ro sc 02
agere systems inc. 55 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 45. phy status register?address 26 phy status register bit name description type default notes 15 reserved ? ? ? ? 14:13 autonegotiation fault status 10 = master/slave autonegotiation fault. 01 = parallel detect autonegotiation fault. 00 = no autonegotiation fault. ro 00 ? 12 autonegotiation status 1 = autonegotiation is complete. 0 = autonegotiation not complete. ro 0 ? 11 mdi-x status 1 = mdi-x configuration. 0 = mdi configuration. ro 0 ? 10 polarity status 1 = polarity is normal (10base-t only). 0 = polarity is inverted (10base-t only). ro 1 ? 9:8 speed status 11 = undetermined. 10 = 1000base-t. 01 = 100base-tx. 00 = 10base-t. ro 11 ? 7 duplex status 1 = full duplex. 0 = half duplex. ro 0 ? 6 link status 1 = link is up. 0 = link is down. ro 0 ? 5 transmit status 1 = phy is transmitting a packet. 0 = phy is not transmitting a packet. ro 0 ? 4 receive status 1 = phy is receiving a packet. 0 = phy is not receiving a packet. ro 0 ? 3 collision status 1 = collision is occurring. 0 = collision not occurring. ro 0 ? 2 autonegotiation enabled 1 = both partners have autonegotiation enabled. 0 = both partners do not have autonegotiation enabled. ro 0 ? 1 pause enabled 1 = link partner advertised pause mode enabled. 0 = link partner adverti sed pause mode disabled. ro 0 ? 0 asymmetric direc- tion 1 = link partner advertised direction is symmetric. 0 = link partner advertised that direction is asym- metric. ro 0 ?
56 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 46. led control register 1?address 27 1. not applicable in the 84-pin or 68-pin mlcc. led control register 1 bit name description type default notes 15:14 reserved ? ? ? ? 13:12 duplex indication led 00 = full duplex. 01 = blink. 10 = on. 11 = off. r/w 00 1 11:10 10base-t led 00 = 10base-t operation. 01 = blink. 10 = on. 11 = off. r/w 00 1 9:8 collision indica- tion led 00 = collision indication. 01 = blink. 10 = on. 11 = off. r/w 00 1 7:6 reserved ? ? ? ? 5.4 reserved ? ? ? ? 3:2 led pulse dura- tion 00 = stretch led events to 28 ms. 01 = stretch led events to 60 ms. 10 = stretch led events to 100 ms. 11 = reserved. r/w 00 ? 1 reserved ? ? ? ? 0 pulse stretch 0 1 = enable pulse stretching of led functions: transmit activity, receive activity, and collision. 0 = disable pulse stretchi ng of led functions: transmit activity, receive activity, and collision. r/w 1 ?
agere systems inc. 57 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 register description (continued) register functions/settings (continued) table 47. led control register 2?address 28 1. not applicable in the 84-pin or 68-mlcc. table 48. reserved registers?addresses 29?31 led control register 2 bit name description type default notes 15:12 transmit/ receive led 0000 = 1000base-t. 0001 = 100base-tx. 0010 = 10base-t. 0011 = 1000base-t on, 100base-tx blink. 0100 = link established. 0101 = transmit. 0110 = receive. 0111 = transmit or receive activity. 1000 = full duplex. 1001 = collision. 1010 = link established (on) and activity (blink). 1011 = link established (on) and receive (blink). 1100 = full duplex (on) and collision (blink). 1101 = blink. 1110 = on. 1111 = off. r/w 0111 1 11:8 link led as per 15:12. r/w 0100 ? 7:4 100base-tx led as per 15:12. r/w 0001 1 3:0 1000base-t led as per 15:12. r/w 0000 ? reserved registers bit name description type default notes 15:0 reserved ? ? ? ?
58 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely af fect device reliability. recommended operating conditions 1. the et1011 is available in 1.0 v and 1.1 v versions. 2. the part can operate at either 3.3 v (typically for an gmii interface) or 2.5 v (typically for an rgmii interface). table 49. absolute maximum ratings parameter symbol min max unit supply voltage (2.5 v analog) av ddh ? 4.2 v supply voltage (1.0 v analog) av ddl ? 1.2 v supply voltage (3.3 v/2.5 v digital) dv ddio ? 4.2 v supply voltage (1.0 v digital) v dd ? 1.2 v esd protection v esd ? 2000 v storage temperature t store ?40 125 c table 50. et1011n0 and et1011r0 recommended operating conditions 1 parameter symbol min typ max unit supply voltage (2.5 v analog) av ddh 2.38 2.5 2.62 v supply voltage (1.0 v analog) av ddl 0.95 1.0 1.05 v supply voltage (3.3 v digital) 2 dv ddio 3.14 3.3 3.46 v supply voltage (2.5 v digital) 2 dv ddio 2.38 2.5 2.62 v supply voltage (1.0 v digital) v dd 0.95 1.0 1.15 v ambient operating temperature?commercial t a 0?70c ambient operating temp erature?industrial t a ?40 ? 85 c maximum junction temperature t j 0?125c thermal characteristics, 128 tqfp (jdec 3 in. x 4.5 in. 4-layer pcb): 0 m/s airflow 1 m/s airflow 2.5 m/s airflow t jb t jc jt ? ? ? 29 33 1 ? ? ? c/w t ja ?37? t ja ?32? t ja ?30? thermal characteristics, 84-pin mlcc and 68 mlcc (jdec 3 in. x 4.5 in. 4-layer pcb): 0 m/s airflow 1 m/s airflow 2.5 m/s airflow t jb t jc jt ? ? ? 10 3 1 ? ? ? c/w t ja ?24? t ja ?23 t ja ?21?
agere systems inc. 59 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications (continued) recommended operating conditions (continued) 1. the et1011 is available in 1.0 v and 1.1 v versions. 2. the part can operate at either 3.3 v (typically for an gm ii interface) or 2.5 v (typically for an rgmii interface). table 51. et1011n1 and et1011r1 recommended operating conditions 1 parameter symbol min typ max unit supply voltage (2.5 v analog) av ddh 2.38 2.5 2.62 v supply voltage (1.0 v analog) av ddl 1.05 1.1 1.15 v supply voltage (3.3 v digital) 2 dv ddio 3.14 3.3 3.46 v supply voltage (2.5 v digital) 2 dv ddio 2.38 2.5 2.62 v supply voltage (1.0 v digital) v dd 1.05 1.1 1.15 v ambient operating temperature?commercial t a 0?70c ambient operating temperature?industrial t a ?40 ? 85 c maximum junction temperature t j 0?125c thermal characteristics, 128 tqfp (jdec 3 in. x 4.5 in. 4-layer pcb): 0 m/s airflow 1 m/s airflow 2.5 m/s airflow t jb t jc jt ? ? ? 29 33 1 ? ? ? c/w t ja ?37? t ja ?32? t ja ?30? thermal characteristics, 84-pin mlcc and 68 mlcc (jdec 3 in. x 4.5 in. 4-layer pcb): 0 m/s airflow 1 m/s airflow 2.5 m/s airflow t jb t jc jt ? ? ? 10 3 1 ? ? ? c/w t ja ?24? t ja ?23 t ja ?21?
60 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications (continued) device electrical characteristics device electrical characterist ics refer to the behavior of the device unde r specified conditions imposed on the user for proper operation of the device. unless otherwise note d, the parameters below are valid for the conditions described in the previous section, recommended operating conditions. table 52. device characteristics?3.3 v digital i/o supply (dv ddio ) parameter symbol min typ max unit input low voltage (gmii input pins) v il ?0.3 ? 0.8 v input low voltage (all other digital input pins) v il ?0.3 ? 0.8 v input high voltage (gmii input pins) v ih 2.0 ? 3.6 v input high voltage (all other digital input pins) v ih 2.0 ? 3.6 v output low voltage (gmii output pins) v ol ? ? 0.4 v output low voltage (all other digital output pins) v ol ? ? 0.4 v output high voltage (gmii output pins) v oh 2.4 ? ? v output high voltage (all other digital output pins) v oh 2.4 ? ? v differential output voltage (analog mdi pins 1000base-t) v odiff 0.67 0.75 0.82 v differential output voltage (analog mdi pins 100base-tx) v odiff 0.95 1.0 1.05 v differential output voltage (analog mdi pins 10base-t) v odiff 2.2 2.5 2.8 v bias voltage v bias ?1.2? v table 53. device characteristics?2.5 v digital i/o supply (dv ddio ) parameter symbol min typ max unit input low voltage (gmii input pins) v il ?0.3 ? 0.7 v input low voltage (all other digital input pins) v il ?0.3 ? 0.7 v input high voltage (gmii input pins) v ih 1.7 ? 2.8 v input high voltage (all other digital input pins) v ih 1.7 ? 2.8 v output low voltage (gmii output pins) v ol ? ? 0.4 v output low voltage (all other digital output pins) v ol ? ? 0.4 v output high voltage (gmii output pins) v oh 2.0 ? ? v output high voltage (all other digital output pins) v oh 2.0 ? ? v differential output voltage (analog mdi pins 1000base-t) v odiff 0.67 0.75 0.82 v differential output voltage (analog mdi pins 100base-tx) v odiff 0.95 1.0 1.05 v differential output voltage (analog mdi pins 10base-t) v odiff 2.2 2.5 2.8 v bias voltage v bias ?1.2? v
agere systems inc. 61 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications (continued) device electrical characteristics (continued) table 54. et1011n0 and et1011r0 current consumption gmii 1000base-t table 55. et1011n0 and et1011r0 current consumption gmii 100base-tx table 56. et1011n0 and et1011r0 current consumption gmii 10base-t parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?59?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?175?ma supply voltage (3.3 v digital) i dvddio tx/rx random data ?42?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?135?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?163?ma parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?20?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?69?ma supply voltage (3.3 v digital) i dvddio tx/rx random data ?27?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?26?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?41?ma parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?26?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?69?ma supply voltage (3.3 v digital) i dvddio tx/rx random data ?19?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?14?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?57?ma
62 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications (continued) device electrical characteristics (continued) table 57. et1011n0 and et1011r0 cu rrent consumption gmii 10base-t idle parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh idle ? 26 ? ma supply voltage (1.0 v analog) i avddl idle ? 69 ? ma supply voltage (3.3 v digital) i dvddio idle ? 15 ? ma supply voltage (1.0 v digital) i vdd idle ? 12 ? ma center tap voltage (1.8 v analog) i ctap idle ? 1 ? ma table 58. et1011n0 and et1011r0 current consumption rgmii 1000base-t parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?59?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?175?ma supply voltage (2.5 v digital) i dvddio tx/rx random data ?24?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?135?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?163?ma table 59. et1011n0 and et1011r0 current consumption rgmii 100base-tx parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?20?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?69?ma supply voltage (2.5 v digital) i dvddio tx/rx random data ?10?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?26?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?41?ma
agere systems inc. 63 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications (continued) device electrical characteristics (continued) table 60. et1011n0 and et1011r0 current consumption rgmii 10base-t parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?26?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?69?ma supply voltage (2.5 v digital) i dvddio tx/rx random data ?7?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?14?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?57?ma table 61. et1011n0 and et1011r0 current consumption rgmii 10base-t idle parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh idle ? 26 ? ma supply voltage (1.0 v analog) i avddl idle ? 69 ? ma supply voltage (2.5 v digital) i dvddio idle ? 7 ? ma supply voltage (1.0 v digital) i vdd idle ? 12 ? ma center tap voltage (1.8 v analog) i ctap idle ? 1 ? ma
64 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications (continued) device electrical characteristics (continued) table 62. et1011n1 and et1011r1 current consumption gmii 1000base-t table 63. et1011n1 and et1011r1 current consumption gmii 100base-tx table 64. et1011n1 and et1011r1 current consumption gmii 10base-t parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?59?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?192?ma supply voltage (3.3 v digital) i dvddio tx/rx random data ?42?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?148?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?163?ma parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?20?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?76?ma supply voltage (3.3 v digital) i dvddio tx/rx random data ?27?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?29?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?41?ma parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?26?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?76?ma supply voltage (3.3 v digital) i dvddio tx/rx random data ?19?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?15?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?57?ma
agere systems inc. 65 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications (continued) device electrical characteristics (continued) table 65. et1011n1 and et1011r1 current consumption gmii 10base-t idle parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh idle ? 26 ? ma supply voltage (1.0 v analog) i avddl idle ? 76 ? ma supply voltage (3.3 v digital) i dvddio idle ? 15 ? ma supply voltage (1.0 v digital) i vdd idle ? 13 ? ma center tap voltage (1.8 v analog) i ctap idle ? 1 ? ma table 66. et1011n1 and et1011r1 current consumption rgmii 1000base-t parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?59?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?192?ma supply voltage (2.5 v digital) i dvddio tx/rx random data ?24?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?148?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?163?ma table 67. et1011n1 and et1011r1 current consumption rgmii 100base-tx parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?20?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?76?ma supply voltage (2.5 v digital) i dvddio tx/rx random data ?10?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?29?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?41?ma
66 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 electrical specifications (continued) device electrical characteristics (continued) table 68. et1011n1 and et1011r1 current consumption rgmii 10base-t parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh tx/rx random data ?26?ma supply voltage (1.0 v analog) i avddl tx/rx random data ?76?ma supply voltage (2.5 v digital) i dvddio tx/rx random data ?7?ma supply voltage (1.0 v digital) i vdd tx/rx random data ?15?ma center tap voltage (1.8 v analog) i ctap tx/rx random data ?57?ma table 69. et1011n1 and et1011r1 current consumption rgmii 10base-t idle parameter symbol condition min typ max unit supply voltage (2.5 v analog) i avddh idle ? 26 ? ma supply voltage (1.0 v analog) i avddl idle ? 76 ? ma supply voltage (2.5 v digital) i dvddio idle ? 7 ? ma supply voltage (1.0 v digital) i vdd idle ? 13 ? ma center tap voltage (1.8 v analog) i ctap idle ? 1 ? ma
agere systems inc. 67 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specification gmii 1000base-t transmit timing (128-pin tqfp only) figure 15. gmii 1000base-t transmit timing table 70. gmii 1000base-t transmit timing parameter symbol min typ max unit gtx_clk cycle time gtx_clk cycle 7.5 ? 8.5 ns gtx_clk high time gtx_clk high 2.5 ? ? ns gtx_clk low time gtx_clk low 2.5 ? ? ns gtx_clk rise time gtx_clk rise ??1.0ns gtx_clk fall time gtx_clk fall ??1.0ns gmii input signal setup time to gtx_clk gtx_clk su 2.0 ? ? ns gmii input signal hold time to gtx_clk gtx_clk hold 0.0 ? ? ns gtx_clk su gtx_clk hold gtx_clk rise gtx_clk fall gtx_clk high gtx_clk cycle gtx_clk low gtx_clk txd[7:0] tx_en tx_er
68 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) gmii 1000base-t receive timing (128-pin tqfp only) figure 16. gmii 1000base-t receive timing table 71. gmii 1000base-t receive timing parameter symbol min typ max unit rx_clk cycle time rx_clk cycle 7.5 8.0 ? ns rx_clk high time rx_clk high 2.5 ? ? ns rx_clk low time rx_clk low 2.5 ? ? ns rx_clk rise time rtx_clk rise ??1.0ns rx_clk fall time rx_clk fall ??1.0ns gmii output signal setup time to rx_clk rx_clk su 2.5 ? ? ns gmii output signal hold time to rx_clk rx_clk hold 0.5 ? ? ns rx_clk su rx_clk hold rx_clk rise rx_clk fall rx_clk high rx_clk cycle rx_clk low rx_clk rxd[7:0] rx_en rx_er
agere systems inc. 69 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) rgmii 1000base-t transmit timing trace delay figure 17. rgmii 1000base-t transmit timing?trace delay table 72. rgmii 1000base-t transmit timing 1. this implies that pcb design will require clocks to be r outed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. to enabl e internal delay, see mii register 22 bits 2:0. 2. for 10base-t and 100base-tx, tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. duty cycle may be shrunk/stretched duri ng speed changes or while transitioning to a received packet?s clock domain as long a s minimum duty cycle is not violated and stretching occurs for no more than three tcyc of the lowest speed transitioned between. parameter symbol min typ max unit data to clock output sk ew (at transmitter)?trace delay 1 tskewt ?500 0 500 ps data to clock input skew (at receiver)?trace delay 1 tskewr 1 1.8 2.6 ns clock cycle duration 2 tcyc 7.2 8 8.8 ns duty cycle for gigabit 3 duty_g 45 50 55 % duty cycle for 10base-t/100base-tx 3 duty_t 40 50 60 % rise/fall time (20%?80%) tr/tf ? ? 0.75 ns tx_clk at transmitter tskewr txd[8:5][3:0] txd[7:4][3:0] txd[8:5] txd[7:4] txd[3:0] tx_ctl tx_clk at receiver txd[4] tx_en txd[9] tx_er tskewt gtx_clk (txc) (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_en (tx_ctl) gtx_clk (txc) (at receiver) txd[4] txen txd[9] txerr txd[3:0] txd[8:5] txd[7:4] tskewt tskewr txc at transmitter txc at receiver
70 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) internal delay figure 18. rgmii 1000base-t tran smit timing?internal delay table 73. rgmii 1000base-t transmit timing 1. the phy uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2.0 ns. 2. for 10base-t and 100base-tx, tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. duty cycle may be shrunk/stretched duri ng speed changes or while transitioning to a re ceived packet?s clock domain as long a s minimum duty cycle is not violated and stretching occurs for no more than three tcyc of the lowest speed transitioned between. parameter symbol min typ max unit data to clock output setup (at transmitter?integrated delay) 1 tsetupt 1.2 2.0 ? ns clock to data output hold (at transmitter?integrated delay) 1 tholdt 1.2 2.0 ? ns data to clock input setup (at receiver?integrated delay) 1 tsetupr 1.0 2.0 ? ns data to clock input setup (at receiver?integrated delay) 1 tholdr 1.0 2.0 ? ns clock cycle duration 2 tcyc 7.2 8 8.8 ns duty cycle for gigabit 3 duty_g 45 50 55 % duty cycle for 10 base-t/100base-tx 3 duty_t 40 50 60 % rise/fall time (20%?80%) tr/tf ? ? 0.75 ns tx_clk at transmitter tskewr txd[8:5][3:0] txd[7:4][3:0] txd[8:5] txd[7:4] txd[3:0] tx_ctl tx_clk at receiver txd[4] tx_en txd[9] tx_er tskewt gtx_clk (txc) (at transmitter) txd[8:5][3:0] txd[7:4][3:0] tx_en (tx_ctl) gtx_clk (txc) (at receiver) txd[4] txen txd[9] txerr tholdt tsetupt txd[3:0] txd[8:5] txd[7:4] txc with internal delay added tsetupr tholdr txc at receiver txc at transmitter txc with internal delay added
agere systems inc. 71 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) rgmii 1000base-t receive timing trace delay figure 19. rgmii 1000base-t receive timing?trace delay table 74. rgmii 1000base-t receive timing 1. this implies that pcb design will require clocks to be r outed such that an additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. to enabl e internal delay, see mii register 22 bits 2:0. 2. for 10base-t and 100base-tx, tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. duty cycle may be shrunk/stretched duri ng speed changes or while transitioning to a received packet?s clock domain as long a s minimum duty cycle is not violated and stretching occurs for no more than three tcyc of the lowest speed transitioned between. parameter symbol min typ max unit data to clock output sk ew (at transmitter)?trace delay 1 tskewt ?500 0 500 ps data to clock input skew (at receiver)?trace delay 1 tskewr 1 1.8 2.6 ns clock cycle duration 2 tcyc 7.2 8 8.8 ns duty cycle for gigabit 3 duty_g 45 50 55 % duty cycle for 10base-t/100base-tx 3 duty_t 40 50 60 % rise/fall time (20%?80%) tr/tf ? ? 0.75 ns rx_clk a t transmitter tskewr rxd[3:0] rxd[3:0] rxd[7:4] rx_ctl rx_clk at receiver tx_en rx_er tskewt rx_clk (rxc) (at transmitter) rxd[8:5][3:0] rxd[7:4][3:0] rx_en (rx_ctl) rx_clk (rxc) (at receiver) rxd[4] rx_dv rxd[9] rxerr rxd[3:0] rxd[8:5] rxd[7:4] tskewt tskewr rxc at transmitter rxc at receiver
72 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) internal delay figure 20. rgmii 1000base-t receive timing?internal delay table 75. rgmii 1000base-t receive timing 1. the phy uses internal delay to compensate by delaying both incoming and outgoing clocks by ~2.0 ns. 2. for 10base-t and 100base-tx, tcyc scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 3. duty cycle may be shrunk/stretched dur ing speed changes or while transitioning to a received packet?s clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three tcyc of the lowest speed transitioned between. parameter symbol min typ max unit data to clock output setup (at transmitter?integrated delay) 1 tsetupt 1.2 2.0 ? ns clock to data output hold (at transmitter?integrated delay) 1 tholdt 1.2 2.0 ? ns data to clock input setup (at receiver?integrated delay) 1 tsetupr 1.0 2.0 ? ns data to clock input setup (at receiver?integrated delay) 1 tholdr 1.0 2.0 ? ns clock cycle duration 2 tcyc 7.2 8 8.8 ns duty cycle for gigabit 3 duty_g 45 50 55 % duty cycle for 10 base-t/100base-tx 3 duty_t 40 50 60 % rise/fall time (20%?80%) tr/tf ? ? 0.75 ns rx_clk a t transmitter tskewr rxd[3:0] rxd[3:0] rxd[7:4] rx_ctl rx_clk at receiver tx_en rx_er tskewt rx_clk (rxc) (at transmitter) rxd[8:5][3:0] rxd[7:4][3:0] rx_en (rx_ctl) rx_clk (rxc) (at receiver) rxd[4] rx_dv rxd[9] rxerr tholdt tsetupt rxd[3:0] rxd[8:5] rxd[7:4] rxc with internal delay added tsetupr tholdr rxc at transmitter rxc at receiver rxd[8:5][3:0] rxd[7:4][3:0] rxc with internal delay added
agere systems inc. 73 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) mii 100base-tx transmit timing 1. tx_er is not available on the 68-pin mlcc. figure 21. mii 100base-tx transmit timing table 76. mii 100base-tx transmit timing parameter symbol min typ max unit tx_clk cycle time tx_clk cycle ?40?ns tx_clk high time tx_clk high ?20?ns tx_clk low time tx_clk low ?20?ns tx_clk rise time tx_clk rise ?? 5 ns tx_clk fall time tx_clk fall ?? 5 ns mii input signal setup time to tx_clk tx_clk su 15 ? ? ns mii input signal hold time to tx_clk tx_clk hold 0??ns tx_clk su tx_clk hold tx_clk rise tx_clk fall tx_clk high tx_clk cycle tx_clk low tx_clk txd[3:0] tx_en tx_er 1
74 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) mii 100base-tx receive timing figure 22. mii 100base-tx receive timing table 77. mii 100base-tx receive timing parameter symbol min typ max unit rx_clk cycle time rx_clk cycle ?40?ns rx_clk high time rx_clk high ?20?ns rx_clk low time rx_clk low ?20?ns rx_clk rise time rtx_clk rise ?1?ns rx_clk fall time rx_clk fall ?1?ns mii output signal setup time to rx_clk rx_clk su 10 ? ? ns mii output signal hold time to rx_clk rx_clk hold 10 ? ? ns rx_clk su rx_clk hold rx_clk rise rx_clk fall rx_clk high rx_clk cycle rx_clk low rx_clk rxd[3:0] rx_en rx_er
agere systems inc. 75 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) mii 10base-t transmit timing figure 23. mii 10base-t transmit timing table 78. mii 10base-t transmit timing parameter symbol min typ max unit tx_clk cycle time tx_clk cycle ? 400 ? ns tx_clk high time tx_clk high ? 200 ? ns tx_clk low time tx_clk low ? 200 ? ns tx_clk rise time tx_clk rise ?1?ns tx_clk fall time tx_clk fall ?1?ns mii input signal setup time to tx_clk tx_clk su 15 ? ? ns mii input signal hold time to tx_clk tx_clk hold 0??ns tx_clk su tx_clk hold tx_clk rise tx_clk fall tx_clk high tx_clk cycle tx_clk low tx_clk txd[3:0] tx_en tx_er
76 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) mii 10base-t receive timing figure 24. mii 10base-t receive timing table 79. mii 10base-t receive timing parameter symbol min typ max unit rx_clk cycle time rx_clk cycle ? 400 ? ns rx_clk high time rx_clk high ? 200 ? ns rx_clk low time rx_clk low ? 200 ? ns rx_clk rise time rtx_clk rise ?1?ns rx_clk fall time rx_clk fall ?1?ns mii output signal setup time to rx_clk rx_clk su 10 ? ? ns mii output signal hold time to rx_clk rx_clk hold 10 ? ? ns rx_clk su rx_clk hold rx_clk rise rx_clk fall rx_clk high rx_clk cycle rx_clk low rx_clk rxd[3:0] rx_en rx_er
agere systems inc. 77 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) serial management interface timing figure 25. serial management interface timing table 80. serial manage ment interface timing parameter symbol min typ max unit mdc cycle time mdc cycle 100 ? ? ns mdc high time mdc high 40 ? ? ns mdc low time mdc low 40 ? ? ns mdc rise time mdc rise ?? 5 ns mdc fall time mdc fall ?? 5 ns mdio signal setup time to mdc mdc su 10 ? ? ns mdio signal hold time to mdc mdc hold 10 ? ? ns mdio delay time from mdc mdc delay ??80ns mdc delay mdc su mdc rise mdio (input) mdc low mdc high mdc hold mdc cycle mdio (output) mdc mdc
78 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) reset timing figure 26. reset timing table 81. reset timing parameter symbol min typ max unit reset_n pulse length reset pulse_len 20 ? ? s reset_n rise time reset rise ?1.0? ns reset_n deassertion to configuration read reset cfg_read ??5.0ms coma pulse length coma pulse_len 20 ? ? s coma fall time coma fall ?1.0? ns coma deassertion to sys_clk coma to_sysclk ?1.0? s coma deassertion to sys_clk valid coma to_sysclk_valid ??4.2ms coma deassertion to configuration read coma cfg_read ??5.0ms reset pulse_len reset rise reset_n sysclk coma pulse_len coma fall coma sysclk coma cfg_read reset cfg_read coma to_sysclk led_xx led pins are inputs led pins are outputs led_xx led pins are inputs led pins are outputs coma to_sysclk_valid
agere systems inc. 79 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) clock timing figure 27. clock timing table 82. clock timing parameter symbol min typ max unit xtal_1 cycle time xtal_1 cycle 39.998 40 40.002 ns xtal_1 high time xtal_1 high 15 20 25 ns xtal_1 low time xtal_1 low 15 20 25 ns xtal_1 rise time xtal_1 rise ?? 3 ns xtal_1 fall time xtal_1 fall ?? 3 ns xtal_1 input clock jitter (rms) ? ? ? 20 ps xtal_1 input clock frequency ? ? 25 ? mhz xtal_1 input clock accuracy ? ? ? 50 ppm xtal_1 cycle xtal_1 high xtal_1 low xtal_1 fall xtal_1 rise xtal_1
80 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 timing specifications (continued) jtag timing figure 28. jtag timing table 83. jtag timing parameter symbol min typ max unit tck cycle time tck cycle 20 ? ? ns tck high time tck high 10 ? ? ns tck low time tck low 10 ? ? ns tck rise time tck rise ?1?ns tck fall time tck fall ?1?ns tdi, tms setup time to tck tck su 2.7 ? ? ns tdi, tms hold time to tck tck hold 0.8 ? ? ns tdo delay time from tck tck delay ??8.1ns tck high tck low tck rise tck fall tck su tck hold tck delay tck tdi tms tdo tck cycle
agere systems inc. 81 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 package diagram, 128-pin tqfp detail a detail b 1.60 max 0.50 typ seating plane 0.08 1.40 0.05 0.05/0.15 1 38 65 102 103 128 pin #1 identifier zone 16.00 0.20 14.00 0.20 20.00 0.20 22.00 0.20 64 39 0.19/0.27 0.08 m 0.106/0.200 0.25 0.45/0.75 1.00 ref gage plane seating plane detail a
82 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 package diagram, 84-pin mlcc (dimensions are in millimeters.) note : package outlines are unofficial and for reference only.
agere systems inc. 83 preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 package diagram, 68-pin mlcc (dimensions are in millimeters.) note : package outlines are unofficial and for reference only.
84 agere systems inc. preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 ordering information table 84. chip set names and part numbers related product documentation device description part number comcode et1011-128 gigabit transceiver, 1.1 v internal regulator, lead et1011r1b-t-db 700079700 et1011-128 gigabit transceiver, 1.1 v internal regulator, lead free l-et1011r1b-t-db 700079850 et1011-68 gigabit transceiver, 1.1 v internal regulator, lead et1011r1b-m-d 700079699 et1011-68 gigabit transceiver, 1.1 v internal regulator, lead free l-et1011r1b-m-d 700079849 et1011-84 gigabit transceiver, 1.1 v internal regulator, lead et1011r1b-c-d 700083637 et1011-84 gigabit transceiver, 1.1 v internal regulator, lead free L-ET1011R1B-C-D 700083636 et1011-84_i gigabit transceiver, 1.1 v internal regulator, lead et1011r1b-ci-d 700081204 et1011-84_i gigabit transceiver, 1.1 v internal regulator, lead free l-et1011r1b-ci-d 700083138 et1011 84-mlcc customer evaluation board et1011-evb 700085008 et1011 68-mlcc gigeasy ? customer evaluation board et1011-usb 700079694 table 85. related product documentation device description document type et1011 gigabit ethernet transceiver product brief application note et1310 gigabit ethernet controller product brief data sheet application note et1081 gigabit ethernet octal phy et4028-50 single-chip 28 x 1 gbit /s layer 2+ ethernet switch et4048-50 single-chip 48 x 1 gbit /s layer 2+ ethernet switch et4128-50 single-chip 28 x 1 gbit/s + 2 x 10 gbits/s layer 2+ ethernet switch et4148-50 single-chip 48 x 1 gbit/s + 2 x 10 gbits/s layer 2+ ethernet switch et3028-50 single-chip 28 x 1 gbit/s layer 2 ethernet switch et3048-50 single-chip 48 x 1 gbit/s layer 2 ethernet switch
preliminary data sheet august 2005 gigabit ethernet transceiver truephy et1011 copyright ? 2005 agere systems inc. all rights reserved august 2005 ds05-181gphy (replaces ds05-131gphy) agere systems inc. reserves the right to make changes to the pr oduct(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are registered trademarks of agere systems inc. gigeasy is a trademark of agere systems inc. for additional information, contact your a gere systems account manager or the following: internet: home: http://www.agere.com sales: http://www.agere.com/sales e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, room 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: china: (86) 21-54614688 (shanghai), (86) 755-25881122 (shenzhen), (86) 10-65391096 (beijing) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6741-9855 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 1344 296 400 ieee is a registered trademark of the institute of electrical and electronics engineers, inc. magic packet is a registered trademark of advanced micro devices, inc.

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